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https://github.com/ARM-software/arm-trusted-firmware.git
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f91c3cb1df
Xilinx is introducing Versal, an adaptive compute acceleration platform (ACAP), built on 7nm FinFET process technology. Versal ACAPs combine Scalar Processing Engines, Adaptable Hardware Engines, and Intelligent Engines with leading-edge memory and interfacing technologies to deliver powerful heterogeneous acceleration for any application. The Versal AI Core series has five devices, offering 128 to 400 AI Engines. The series includes dual-core Arm Cortex-A72 application processors, dual-core Arm Cortex-R5 real-time processors, 256KB of on-chip memory with ECC, more than 1,900 DSP engines optimized for high-precision floating point with low latency. This patch adds Virtual QEMU platform support for this SoC "versal_virt". Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
64 lines
2.0 KiB
Makefile
64 lines
2.0 KiB
Makefile
# Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
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#
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# SPDX-License-Identifier: BSD-3-Clause
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override PROGRAMMABLE_RESET_ADDRESS := 1
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PSCI_EXTENDED_STATE_ID := 1
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A53_DISABLE_NON_TEMPORAL_HINT := 0
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SEPARATE_CODE_AND_RODATA := 1
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override RESET_TO_BL31 := 1
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PL011_GENERIC_UART := 1
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MULTI_CONSOLE_API := 1
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ifdef VERSAL_ATF_MEM_BASE
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$(eval $(call add_define,VERSAL_ATF_MEM_BASE))
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ifndef VERSAL_ATF_MEM_SIZE
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$(error "VERSAL_ATF_BASE defined without VERSAL_ATF_SIZE")
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endif
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$(eval $(call add_define,VERSAL_ATF_MEM_SIZE))
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ifdef VERSAL_ATF_MEM_PROGBITS_SIZE
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$(eval $(call add_define,VERSAL_ATF_MEM_PROGBITS_SIZE))
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endif
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endif
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ifdef VERSAL_BL32_MEM_BASE
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$(eval $(call add_define,VERSAL_BL32_MEM_BASE))
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ifndef VERSAL_BL32_MEM_SIZE
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$(error "VERSAL_BL32_BASE defined without VERSAL_BL32_SIZE")
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endif
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$(eval $(call add_define,VERSAL_BL32_MEM_SIZE))
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endif
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VERSAL_PLATFORM ?= versal_virt
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$(eval $(call add_define_val,VERSAL_PLATFORM,VERSAL_PLATFORM_ID_${VERSAL_PLATFORM}))
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VERSAL_CONSOLE ?= pl011
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$(eval $(call add_define_val,VERSAL_CONSOLE,VERSAL_CONSOLE_ID_${VERSAL_CONSOLE}))
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PLAT_INCLUDES := -Iplat/xilinx/versal/include/
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PLAT_BL_COMMON_SOURCES := lib/xlat_tables/xlat_tables_common.c \
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lib/xlat_tables/aarch64/xlat_tables.c \
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drivers/delay_timer/delay_timer.c \
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drivers/delay_timer/generic_delay_timer.c \
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drivers/arm/gic/common/gic_common.c \
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drivers/arm/gic/v3/gicv3_main.c \
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drivers/arm/gic/v3/gicv3_helpers.c \
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drivers/arm/pl011/aarch64/pl011_console.S \
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plat/common/plat_gicv3.c \
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plat/xilinx/versal/aarch64/versal_helpers.S \
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plat/xilinx/versal/aarch64/versal_common.c
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BL31_SOURCES += lib/cpus/aarch64/cortex_a53.S \
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lib/cpus/aarch64/cortex_a72.S \
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plat/common/plat_psci_common.c \
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plat/xilinx/versal/bl31_versal_setup.c \
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plat/xilinx/versal/plat_psci.c \
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plat/xilinx/versal/plat_versal.c \
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plat/xilinx/versal/plat_topology.c \
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plat/xilinx/versal/sip_svc_setup.c \
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plat/xilinx/versal/versal_gicv3.c
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