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09d40e0e08
Enforce full include path for includes. Deprecate old paths.
The following folders inside include/lib have been left unchanged:
- include/lib/cpus/${ARCH}
- include/lib/el3_runtime/${ARCH}
The reason for this change is that having a global namespace for
includes isn't a good idea. It defeats one of the advantages of having
folders and it introduces problems that are sometimes subtle (because
you may not know the header you are actually including if there are two
of them).
For example, this patch had to be created because two headers were
called the same way: e0ea0928d5b7 ("Fix gpio includes of mt8173 platform
to avoid collision."). More recently, this patch has had similar
problems: 46f9b2c3a282 ("drivers: add tzc380 support").
This problem was introduced in commit 4ecca33988b9 ("Move include and
source files to logical locations"). At that time, there weren't too
many headers so it wasn't a real issue. However, time has shown that
this creates problems.
Platforms that want to preserve the way they include headers may add the
removed paths to PLAT_INCLUDES, but this is discouraged.
Change-Id: I39dc53ed98f9e297a5966e723d1936d6ccf2fc8f
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
103 lines
3.4 KiB
C
103 lines
3.4 KiB
C
/*
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* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef PLATFORM_DEF_H
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#define PLATFORM_DEF_H
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#include <arch.h>
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#include "../versal_def.h"
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/*******************************************************************************
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* Generic platform constants
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******************************************************************************/
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/* Size of cacheable stacks */
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#define PLATFORM_STACK_SIZE 0x440
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#define PLATFORM_CORE_COUNT 2
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#define PLAT_MAX_PWR_LVL 1
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#define PLAT_MAX_RET_STATE 1
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#define PLAT_MAX_OFF_STATE 2
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/*******************************************************************************
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* BL31 specific defines.
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******************************************************************************/
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/*
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* Put BL31 at the top of the Trusted SRAM (just below the shared memory, if
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* present). BL31_BASE is calculated using the current BL31 debug size plus a
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* little space for growth.
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*/
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#ifndef VERSAL_ATF_MEM_BASE
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# define BL31_BASE 0xfffea000
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# define BL31_LIMIT 0xffffffff
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#else
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# define BL31_BASE (VERSAL_ATF_MEM_BASE)
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# define BL31_LIMIT (VERSAL_ATF_MEM_BASE + VERSAL_ATF_MEM_SIZE - 1)
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# ifdef VERSAL_ATF_MEM_PROGBITS_SIZE
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# define BL31_PROGBITS_LIMIT (VERSAL_ATF_MEM_BASE + VERSAL_ATF_MEM_PROGBITS_SIZE - 1)
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# endif
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#endif
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/*******************************************************************************
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* BL32 specific defines.
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******************************************************************************/
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#ifndef VERSAL_BL32_MEM_BASE
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# define BL32_BASE 0x60000000
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# define BL32_LIMIT 0x7fffffff
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#else
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# define BL32_BASE (VERSAL_BL32_MEM_BASE)
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# define BL32_LIMIT (VERSAL_BL32_MEM_BASE + VERSAL_BL32_MEM_SIZE - 1)
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#endif
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/*******************************************************************************
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* BL33 specific defines.
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******************************************************************************/
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#ifndef PRELOADED_BL33_BASE
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# define PLAT_VERSAL_NS_IMAGE_OFFSET 0x8000000
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#else
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# define PLAT_VERSAL_NS_IMAGE_OFFSET PRELOADED_BL33_BASE
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#endif
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/*******************************************************************************
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* TSP specific defines.
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******************************************************************************/
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#define TSP_SEC_MEM_BASE BL32_BASE
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#define TSP_SEC_MEM_SIZE (BL32_LIMIT - BL32_BASE + 1)
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/* ID of the secure physical generic timer interrupt used by the TSP */
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#define TSP_IRQ_SEC_PHY_TIMER ARM_IRQ_SEC_PHY_TIMER
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/*******************************************************************************
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* Platform specific page table and MMU setup constants
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******************************************************************************/
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#define PLAT_PHY_ADDR_SPACE_SIZE (1ull << 32)
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#define PLAT_VIRT_ADDR_SPACE_SIZE (1ull << 32)
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#define MAX_MMAP_REGIONS 7
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#define MAX_XLAT_TABLES 5
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#define CACHE_WRITEBACK_SHIFT 6
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#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT)
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#define PLAT_VERSAL_GICD_BASE 0xF9000000
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#define PLAT_VERSAL_GICR_BASE 0xF9080000
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/*
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* Define a list of Group 1 Secure and Group 0 interrupts as per GICv3
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* terminology. On a GICv2 system or mode, the lists will be merged and treated
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* as Group 0 interrupts.
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*/
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#define PLAT_VERSAL_G1S_IRQS VERSAL_IRQ_SEC_PHY_TIMER
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#define PLAT_VERSAL_G0_IRQS VERSAL_IRQ_SEC_PHY_TIMER
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#define PLAT_VERSAL_G1S_IRQ_PROPS(grp) \
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INTR_PROP_DESC(VERSAL_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, grp, \
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GIC_INTR_CFG_LEVEL)
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#define PLAT_VERSAL_G0_IRQ_PROPS(grp)
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#endif /* PLATFORM_DEF_H */
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