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09d40e0e08
Enforce full include path for includes. Deprecate old paths.
The following folders inside include/lib have been left unchanged:
- include/lib/cpus/${ARCH}
- include/lib/el3_runtime/${ARCH}
The reason for this change is that having a global namespace for
includes isn't a good idea. It defeats one of the advantages of having
folders and it introduces problems that are sometimes subtle (because
you may not know the header you are actually including if there are two
of them).
For example, this patch had to be created because two headers were
called the same way: e0ea0928d5 ("Fix gpio includes of mt8173 platform
to avoid collision."). More recently, this patch has had similar
problems: 46f9b2c3a2 ("drivers: add tzc380 support").
This problem was introduced in commit 4ecca33988 ("Move include and
source files to logical locations"). At that time, there weren't too
many headers so it wasn't a real issue. However, time has shown that
this creates problems.
Platforms that want to preserve the way they include headers may add the
removed paths to PLAT_INCLUDES, but this is discouraged.
Change-Id: I39dc53ed98f9e297a5966e723d1936d6ccf2fc8f
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
182 lines
5.1 KiB
ArmAsm
182 lines
5.1 KiB
ArmAsm
/*
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* Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <platform_def.h>
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#include <arch.h>
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#include <asm_macros.S>
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#include <common/bl_common.h>
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#include <drivers/st/stm32_gpio.h>
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#include <drivers/st/stm32mp1_rcc.h>
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#define GPIO_BANK_G_ADDRESS 0x50008000
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#define GPIO_TX_PORT 11
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#define GPIO_TX_SHIFT (GPIO_TX_PORT << 1)
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#define GPIO_TX_ALT_SHIFT ((GPIO_TX_PORT - GPIO_ALT_LOWER_LIMIT) << 2)
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#define STM32MP1_HSI_CLK 64000000
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.globl platform_mem_init
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.globl plat_report_exception
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.globl plat_get_my_entrypoint
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.globl plat_secondary_cold_boot_setup
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.globl plat_reset_handler
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.globl plat_is_my_cpu_primary
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.globl plat_my_core_pos
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.globl plat_crash_console_init
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.globl plat_crash_console_flush
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.globl plat_crash_console_putc
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.globl plat_panic_handler
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func platform_mem_init
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/* Nothing to do, don't need to init SYSRAM */
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bx lr
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endfunc platform_mem_init
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func plat_report_exception
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bx lr
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endfunc plat_report_exception
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func plat_reset_handler
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bx lr
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endfunc plat_reset_handler
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/* ------------------------------------------------------------------
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* unsigned long plat_get_my_entrypoint (void);
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*
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* Main job of this routine is to distinguish between a cold and warm
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* boot.
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*
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* Currently supports only cold boot
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* ------------------------------------------------------------------
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*/
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func plat_get_my_entrypoint
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mov r0, #0
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bx lr
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endfunc plat_get_my_entrypoint
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/* ---------------------------------------------
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* void plat_secondary_cold_boot_setup (void);
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*
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* Cold-booting secondary CPUs is not supported.
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* ---------------------------------------------
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*/
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func plat_secondary_cold_boot_setup
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b .
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endfunc plat_secondary_cold_boot_setup
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/* -----------------------------------------------------
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* unsigned int plat_is_my_cpu_primary (void);
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*
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* Find out whether the current cpu is the primary cpu.
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* -----------------------------------------------------
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*/
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func plat_is_my_cpu_primary
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ldcopr r0, MPIDR
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ldr r1, =(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)
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and r0, r1
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cmp r0, #STM32MP1_PRIMARY_CPU
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moveq r0, #1
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movne r0, #0
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bx lr
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endfunc plat_is_my_cpu_primary
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/* -------------------------------------------
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* int plat_stm32mp1_get_core_pos(int mpidr);
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*
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* Return CorePos = (ClusterId * 4) + CoreId
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* -------------------------------------------
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*/
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func plat_stm32mp1_get_core_pos
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and r1, r0, #MPIDR_CPU_MASK
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and r0, r0, #MPIDR_CLUSTER_MASK
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add r0, r1, r0, LSR #6
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bx lr
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endfunc plat_stm32mp1_get_core_pos
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/* ------------------------------------
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* unsigned int plat_my_core_pos(void)
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* ------------------------------------
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*/
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func plat_my_core_pos
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ldcopr r0, MPIDR
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b plat_stm32mp1_get_core_pos
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endfunc plat_my_core_pos
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/* ---------------------------------------------
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* int plat_crash_console_init(void)
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*
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* Initialize the crash console without a C Runtime stack.
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* ---------------------------------------------
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*/
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func plat_crash_console_init
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/* Enable GPIOs for UART4 TX */
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ldr r1, =(RCC_BASE + RCC_MP_AHB4ENSETR)
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ldr r2, [r1]
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/* Configure GPIO G11 */
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orr r2, r2, #RCC_MP_AHB4ENSETR_GPIOGEN
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str r2, [r1]
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ldr r1, =GPIO_BANK_G_ADDRESS
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/* Set GPIO mode alternate */
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ldr r2, [r1, #GPIO_MODE_OFFSET]
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bic r2, r2, #(GPIO_MODE_MASK << GPIO_TX_SHIFT)
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orr r2, r2, #(GPIO_MODE_ALTERNATE << GPIO_TX_SHIFT)
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str r2, [r1, #GPIO_MODE_OFFSET]
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/* Set GPIO speed low */
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ldr r2, [r1, #GPIO_SPEED_OFFSET]
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bic r2, r2, #(GPIO_SPEED_MASK << GPIO_TX_SHIFT)
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str r2, [r1, #GPIO_SPEED_OFFSET]
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/* Set no-pull */
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ldr r2, [r1, #GPIO_PUPD_OFFSET]
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bic r2, r2, #(GPIO_PULL_MASK << GPIO_TX_SHIFT)
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str r2, [r1, #GPIO_PUPD_OFFSET]
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/* Set alternate AF6 */
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ldr r2, [r1, #GPIO_AFRH_OFFSET]
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bic r2, r2, #(GPIO_ALTERNATE_MASK << GPIO_TX_ALT_SHIFT)
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orr r2, r2, #(GPIO_ALTERNATE_6 << GPIO_TX_ALT_SHIFT)
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str r2, [r1, #GPIO_AFRH_OFFSET]
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/* Enable UART clock, with HSI source */
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ldr r1, =(RCC_BASE + RCC_UART24CKSELR)
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mov r2, #RCC_UART24CKSELR_HSI
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str r2, [r1]
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ldr r1, =(RCC_BASE + RCC_MP_APB1ENSETR)
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ldr r2, [r1]
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orr r2, r2, #RCC_MP_APB1ENSETR_UART4EN
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str r2, [r1]
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ldr r0, =STM32MP1_DEBUG_USART_BASE
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ldr r1, =STM32MP1_HSI_CLK
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ldr r2, =STM32MP1_UART_BAUDRATE
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b console_stm32_core_init
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endfunc plat_crash_console_init
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/* ---------------------------------------------
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* int plat_crash_console_flush(void)
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*
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* Flush the crash console without a C Runtime stack.
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* ---------------------------------------------
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*/
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func plat_crash_console_flush
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ldr r1, =STM32MP1_DEBUG_USART_BASE
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b console_stm32_core_flush
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endfunc plat_crash_console_flush
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/* ---------------------------------------------
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* int plat_crash_console_putc(int c)
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*
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* Print a character on the crash console without a C Runtime stack.
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* Clobber list : r1 - r3
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*
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* In case of bootloading through uart, we keep console crash as this.
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* Characters could be sent to the programmer, but will be ignored.
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* No specific code in that case.
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* ---------------------------------------------
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*/
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func plat_crash_console_putc
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ldr r1, =STM32MP1_DEBUG_USART_BASE
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b console_stm32_core_putc
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endfunc plat_crash_console_putc
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