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09d40e0e08
Enforce full include path for includes. Deprecate old paths.
The following folders inside include/lib have been left unchanged:
- include/lib/cpus/${ARCH}
- include/lib/el3_runtime/${ARCH}
The reason for this change is that having a global namespace for
includes isn't a good idea. It defeats one of the advantages of having
folders and it introduces problems that are sometimes subtle (because
you may not know the header you are actually including if there are two
of them).
For example, this patch had to be created because two headers were
called the same way: e0ea0928d5b7 ("Fix gpio includes of mt8173 platform
to avoid collision."). More recently, this patch has had similar
problems: 46f9b2c3a282 ("drivers: add tzc380 support").
This problem was introduced in commit 4ecca33988b9 ("Move include and
source files to logical locations"). At that time, there weren't too
many headers so it wasn't a real issue. However, time has shown that
this creates problems.
Platforms that want to preserve the way they include headers may add the
removed paths to PLAT_INCLUDES, but this is discouraged.
Change-Id: I39dc53ed98f9e297a5966e723d1936d6ccf2fc8f
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
101 lines
2.9 KiB
C
101 lines
2.9 KiB
C
/*
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* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <common/bl_common.h>
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#include <common/desc_image_load.h>
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#include "ls_16550.h"
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#include "plat_ls.h"
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#include "ls_def.h"
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/* Data structure which holds the extents of the trusted SRAM for BL2 */
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static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE);
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/*******************************************************************************
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* BL1 has passed the extents of the trusted SRAM that should be visible to BL2
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* in x0. This memory layout is sitting at the base of the free trusted SRAM.
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* Copy it to a safe location before its reclaimed by later BL2 functionality.
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******************************************************************************/
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void ls_bl2_early_platform_setup(meminfo_t *mem_layout)
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{
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static console_ls_16550_t console;
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/* Initialize the console to provide early debug support */
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console_ls_16550_register(LS_TF_UART_BASE, LS_TF_UART_CLOCK,
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LS_TF_UART_BAUDRATE, &console);
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/* Setup the BL2 memory layout */
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bl2_tzram_layout = *mem_layout;
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/* Initialise the IO layer and register platform IO devices */
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plat_ls_io_setup();
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}
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/*******************************************************************************
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* Perform the very early platform specific architectural setup here. At the
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* moment this is only initializes the mmu in a quick and dirty way.
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******************************************************************************/
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void ls_bl2_plat_arch_setup(void)
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{
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ls_setup_page_tables(bl2_tzram_layout.total_base,
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bl2_tzram_layout.total_size,
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BL_CODE_BASE,
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BL_CODE_END,
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BL_RO_DATA_BASE,
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BL_RO_DATA_END
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#if USE_COHERENT_MEM
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, BL_COHERENT_RAM_BASE,
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BL_COHERENT_RAM_END
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#endif
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);
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#ifdef AARCH32
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enable_mmu_svc_mon(0);
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#else
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enable_mmu_el1(0);
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#endif
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}
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void bl2_plat_arch_setup(void)
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{
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ls_bl2_plat_arch_setup();
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}
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int ls_bl2_handle_post_image_load(unsigned int image_id)
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{
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int err = 0;
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bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id);
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assert(bl_mem_params);
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switch (image_id) {
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#ifdef AARCH64
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case BL32_IMAGE_ID:
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bl_mem_params->ep_info.spsr = ls_get_spsr_for_bl32_entry();
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break;
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#endif
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case BL33_IMAGE_ID:
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/* BL33 expects to receive the primary CPU MPID (through r0) */
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bl_mem_params->ep_info.args.arg0 = 0xffff & read_mpidr();
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bl_mem_params->ep_info.spsr = ls_get_spsr_for_bl33_entry();
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break;
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}
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return err;
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}
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/*******************************************************************************
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* This function can be used by the platforms to update/use image
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* information for given `image_id`.
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******************************************************************************/
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int bl2_plat_handle_post_image_load(unsigned int image_id)
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{
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return ls_bl2_handle_post_image_load(image_id);
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}
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