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09d40e0e08
Enforce full include path for includes. Deprecate old paths.
The following folders inside include/lib have been left unchanged:
- include/lib/cpus/${ARCH}
- include/lib/el3_runtime/${ARCH}
The reason for this change is that having a global namespace for
includes isn't a good idea. It defeats one of the advantages of having
folders and it introduces problems that are sometimes subtle (because
you may not know the header you are actually including if there are two
of them).
For example, this patch had to be created because two headers were
called the same way: e0ea0928d5 ("Fix gpio includes of mt8173 platform
to avoid collision."). More recently, this patch has had similar
problems: 46f9b2c3a2 ("drivers: add tzc380 support").
This problem was introduced in commit 4ecca33988 ("Move include and
source files to logical locations"). At that time, there weren't too
many headers so it wasn't a real issue. However, time has shown that
this creates problems.
Platforms that want to preserve the way they include headers may add the
removed paths to PLAT_INCLUDES, but this is discouraged.
Change-Id: I39dc53ed98f9e297a5966e723d1936d6ccf2fc8f
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
153 lines
3.8 KiB
C
153 lines
3.8 KiB
C
/*
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* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <stdbool.h>
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#include <platform_def.h>
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#include <arch_helpers.h>
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#include <common/bl_common.h>
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#include <common/debug.h>
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#include <context.h>
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#include <drivers/arm/tzc380.h>
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#include <drivers/console.h>
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#include <lib/el3_runtime/context_mgmt.h>
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#include <lib/mmio.h>
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#include <lib/xlat_tables/xlat_tables.h>
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#include <plat/common/platform.h>
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#include <gpc.h>
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#include <imx_uart.h>
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#include <plat_imx8.h>
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IMPORT_SYM(uintptr_t, __COHERENT_RAM_START__, BL31_COHERENT_RAM_START);
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IMPORT_SYM(uintptr_t, __COHERENT_RAM_END__, BL31_COHERENT_RAM_END);
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IMPORT_SYM(uintptr_t, __RO_START__, BL31_RO_START);
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IMPORT_SYM(uintptr_t, __RO_END__, BL31_RO_END);
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IMPORT_SYM(uintptr_t, __RW_START__, BL31_RW_START);
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IMPORT_SYM(uintptr_t, __RW_END__, BL31_RW_END);
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static const mmap_region_t imx_mmap[] = {
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MAP_REGION_FLAT(GPV_BASE, GPV_SIZE, MT_DEVICE | MT_RW), /* GPV map */
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MAP_REGION_FLAT(IMX_AIPS_BASE, IMX_AIPS_SIZE, MT_DEVICE | MT_RW), /* AIPS map */
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MAP_REGION_FLAT(IMX_GIC_BASE, IMX_GIC_SIZE, MT_DEVICE | MT_RW), /* GIC map */
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{0},
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};
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static entry_point_info_t bl32_image_ep_info;
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static entry_point_info_t bl33_image_ep_info;
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/* get SPSR for BL33 entry */
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static uint32_t get_spsr_for_bl33_entry(void)
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{
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unsigned long el_status;
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unsigned long mode;
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uint32_t spsr;
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/* figure out what mode we enter the non-secure world */
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el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT;
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el_status &= ID_AA64PFR0_ELX_MASK;
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mode = (el_status) ? MODE_EL2 : MODE_EL1;
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spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS);
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return spsr;
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}
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static void bl31_tz380_setup(void)
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{
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unsigned int val;
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val = mmio_read_32(IMX_IOMUX_GPR_BASE + IOMUXC_GPR10);
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if ((val & GPR_TZASC_EN) != GPR_TZASC_EN)
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return;
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tzc380_init(IMX_TZASC_BASE);
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/*
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* Need to substact offset 0x40000000 from CPU address when
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* programming tzasc region for i.mx8mq. Enable 1G-5G S/NS RW
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*/
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tzc380_configure_region(0, 0x00000000, TZC_ATTR_REGION_SIZE(TZC_REGION_SIZE_4G) |
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TZC_ATTR_REGION_EN_MASK | TZC_ATTR_SP_ALL);
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}
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void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
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u_register_t arg2, u_register_t arg3)
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{
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int i;
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/* enable CSU NS access permission */
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for (i = 0; i < 64; i++) {
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mmio_write_32(IMX_CSU_BASE + i * 4, 0xffffffff);
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}
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#if DEBUG_CONSOLE
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static console_uart_t console;
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console_uart_register(IMX_BOOT_UART_BASE, IMX_BOOT_UART_CLK_IN_HZ,
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IMX_CONSOLE_BAUDRATE, &console);
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#endif
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/*
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* tell BL3-1 where the non-secure software image is located
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* and the entry state information.
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*/
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bl33_image_ep_info.pc = PLAT_NS_IMAGE_OFFSET;
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bl33_image_ep_info.spsr = get_spsr_for_bl33_entry();
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SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE);
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bl31_tz380_setup();
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}
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void bl31_plat_arch_setup(void)
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{
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mmap_add_region(BL31_RO_START, BL31_RO_START, (BL31_RO_END - BL31_RO_START),
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MT_MEMORY | MT_RO | MT_SECURE);
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mmap_add_region(BL31_RW_START, BL31_RW_START, (BL31_RW_END - BL31_RW_START),
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MT_MEMORY | MT_RW | MT_SECURE);
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mmap_add(imx_mmap);
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#if USE_COHERENT_MEM
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mmap_add_region(BL31_COHERENT_RAM_START, BL31_COHERENT_RAM_START,
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BL31_COHERENT_RAM_END - BL31_COHERENT_RAM_START,
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MT_DEVICE | MT_RW | MT_SECURE);
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#endif
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/* setup xlat table */
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init_xlat_tables();
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/* enable the MMU */
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enable_mmu_el3(0);
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}
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void bl31_platform_setup(void)
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{
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/* init the GICv3 cpu and distributor interface */
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plat_gic_driver_init();
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plat_gic_init();
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/* gpc init */
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imx_gpc_init();
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}
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entry_point_info_t *bl31_plat_get_next_image_ep_info(unsigned int type)
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{
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if (type == NON_SECURE)
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return &bl33_image_ep_info;
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if (type == SECURE)
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return &bl32_image_ep_info;
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return NULL;
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}
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unsigned int plat_get_syscnt_freq2(void)
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{
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return COUNTER_FREQUENCY;
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}
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void bl31_plat_runtime_setup(void)
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{
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return;
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}
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