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09d40e0e08
Enforce full include path for includes. Deprecate old paths.
The following folders inside include/lib have been left unchanged:
- include/lib/cpus/${ARCH}
- include/lib/el3_runtime/${ARCH}
The reason for this change is that having a global namespace for
includes isn't a good idea. It defeats one of the advantages of having
folders and it introduces problems that are sometimes subtle (because
you may not know the header you are actually including if there are two
of them).
For example, this patch had to be created because two headers were
called the same way: e0ea0928d5 ("Fix gpio includes of mt8173 platform
to avoid collision."). More recently, this patch has had similar
problems: 46f9b2c3a2 ("drivers: add tzc380 support").
This problem was introduced in commit 4ecca33988 ("Move include and
source files to logical locations"). At that time, there weren't too
many headers so it wasn't a real issue. However, time has shown that
this creates problems.
Platforms that want to preserve the way they include headers may add the
removed paths to PLAT_INCLUDES, but this is discouraged.
Change-Id: I39dc53ed98f9e297a5966e723d1936d6ccf2fc8f
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
269 lines
6.7 KiB
ArmAsm
269 lines
6.7 KiB
ArmAsm
/*
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* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <assert_macros.S>
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#include <common/debug.h>
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#include <cortex_a53.h>
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#include <cpu_macros.S>
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#if A53_DISABLE_NON_TEMPORAL_HINT
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#undef ERRATA_A53_836870
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#define ERRATA_A53_836870 1
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#endif
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/* ---------------------------------------------
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* Disable intra-cluster coherency
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* ---------------------------------------------
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*/
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func cortex_a53_disable_smp
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ldcopr16 r0, r1, CORTEX_A53_ECTLR
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bic64_imm r0, r1, CORTEX_A53_ECTLR_SMP_BIT
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stcopr16 r0, r1, CORTEX_A53_ECTLR
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isb
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dsb sy
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bx lr
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endfunc cortex_a53_disable_smp
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/* --------------------------------------------------
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* Errata Workaround for Cortex A53 Errata #826319.
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* This applies only to revision <= r0p2 of Cortex A53.
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* Inputs:
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* r0: variant[4:7] and revision[0:3] of current cpu.
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* Shall clobber: r0-r3
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* --------------------------------------------------
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*/
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func errata_a53_826319_wa
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/*
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* Compare r0 against revision r0p2
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*/
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mov r2, lr
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bl check_errata_826319
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mov lr, r2
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cmp r0, #ERRATA_NOT_APPLIES
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beq 1f
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ldcopr r0, CORTEX_A53_L2ACTLR
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bic r0, #CORTEX_A53_L2ACTLR_ENABLE_UNIQUECLEAN
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orr r0, #CORTEX_A53_L2ACTLR_DISABLE_CLEAN_PUSH
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stcopr r0, CORTEX_A53_L2ACTLR
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1:
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bx lr
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endfunc errata_a53_826319_wa
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func check_errata_826319
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mov r1, #0x02
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b cpu_rev_var_ls
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endfunc check_errata_826319
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/* ---------------------------------------------------------------------
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* Disable the cache non-temporal hint.
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*
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* This ignores the Transient allocation hint in the MAIR and treats
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* allocations the same as non-transient allocation types. As a result,
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* the LDNP and STNP instructions in AArch64 behave the same as the
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* equivalent LDP and STP instructions.
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*
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* This is relevant only for revisions <= r0p3 of Cortex-A53.
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* From r0p4 and onwards, the bit to disable the hint is enabled by
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* default at reset.
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*
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* Inputs:
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* r0: variant[4:7] and revision[0:3] of current cpu.
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* Shall clobber: r0-r3
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* ---------------------------------------------------------------------
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*/
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func a53_disable_non_temporal_hint
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/*
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* Compare r0 against revision r0p3
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*/
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mov r2, lr
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bl check_errata_disable_non_temporal_hint
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mov lr, r2
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cmp r0, #ERRATA_NOT_APPLIES
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beq 1f
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ldcopr16 r0, r1, CORTEX_A53_CPUACTLR
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orr64_imm r0, r1, CORTEX_A53_CPUACTLR_DTAH
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stcopr16 r0, r1, CORTEX_A53_CPUACTLR
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1:
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bx lr
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endfunc a53_disable_non_temporal_hint
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func check_errata_disable_non_temporal_hint
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mov r1, #0x03
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b cpu_rev_var_ls
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endfunc check_errata_disable_non_temporal_hint
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/* --------------------------------------------------
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* Errata Workaround for Cortex A53 Errata #855873.
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*
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* This applies only to revisions >= r0p3 of Cortex A53.
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* Earlier revisions of the core are affected as well, but don't
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* have the chicken bit in the CPUACTLR register. It is expected that
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* the rich OS takes care of that, especially as the workaround is
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* shared with other erratas in those revisions of the CPU.
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* Inputs:
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* r0: variant[4:7] and revision[0:3] of current cpu.
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* Shall clobber: r0-r3
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* --------------------------------------------------
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*/
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func errata_a53_855873_wa
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/*
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* Compare r0 against revision r0p3 and higher
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*/
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mov r2, lr
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bl check_errata_855873
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mov lr, r2
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cmp r0, #ERRATA_NOT_APPLIES
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beq 1f
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ldcopr16 r0, r1, CORTEX_A53_CPUACTLR
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orr64_imm r0, r1, CORTEX_A53_CPUACTLR_ENDCCASCI
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stcopr16 r0, r1, CORTEX_A53_CPUACTLR
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1:
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bx lr
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endfunc errata_a53_855873_wa
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func check_errata_855873
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mov r1, #0x03
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b cpu_rev_var_hs
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endfunc check_errata_855873
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/* -------------------------------------------------
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* The CPU Ops reset function for Cortex-A53.
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* Shall clobber: r0-r6
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* -------------------------------------------------
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*/
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func cortex_a53_reset_func
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mov r5, lr
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bl cpu_get_rev_var
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mov r4, r0
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#if ERRATA_A53_826319
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mov r0, r4
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bl errata_a53_826319_wa
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#endif
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#if ERRATA_A53_836870
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mov r0, r4
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bl a53_disable_non_temporal_hint
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#endif
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#if ERRATA_A53_855873
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mov r0, r4
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bl errata_a53_855873_wa
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#endif
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/* ---------------------------------------------
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* Enable the SMP bit.
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* ---------------------------------------------
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*/
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ldcopr16 r0, r1, CORTEX_A53_ECTLR
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orr64_imm r0, r1, CORTEX_A53_ECTLR_SMP_BIT
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stcopr16 r0, r1, CORTEX_A53_ECTLR
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isb
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bx r5
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endfunc cortex_a53_reset_func
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/* ----------------------------------------------------
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* The CPU Ops core power down function for Cortex-A53.
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* ----------------------------------------------------
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*/
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func cortex_a53_core_pwr_dwn
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push {r12, lr}
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/* Assert if cache is enabled */
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#if ENABLE_ASSERTIONS
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ldcopr r0, SCTLR
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tst r0, #SCTLR_C_BIT
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ASM_ASSERT(eq)
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#endif
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/* ---------------------------------------------
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* Flush L1 caches.
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* ---------------------------------------------
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*/
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mov r0, #DC_OP_CISW
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bl dcsw_op_level1
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/* ---------------------------------------------
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* Come out of intra cluster coherency
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* ---------------------------------------------
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*/
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pop {r12, lr}
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b cortex_a53_disable_smp
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endfunc cortex_a53_core_pwr_dwn
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/* -------------------------------------------------------
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* The CPU Ops cluster power down function for Cortex-A53.
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* Clobbers: r0-r3
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* -------------------------------------------------------
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*/
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func cortex_a53_cluster_pwr_dwn
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push {r12, lr}
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/* Assert if cache is enabled */
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#if ENABLE_ASSERTIONS
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ldcopr r0, SCTLR
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tst r0, #SCTLR_C_BIT
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ASM_ASSERT(eq)
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#endif
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/* ---------------------------------------------
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* Flush L1 caches.
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* ---------------------------------------------
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*/
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mov r0, #DC_OP_CISW
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bl dcsw_op_level1
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/* ---------------------------------------------
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* Disable the optional ACP.
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* ---------------------------------------------
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*/
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bl plat_disable_acp
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/* ---------------------------------------------
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* Flush L2 caches.
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* ---------------------------------------------
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*/
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mov r0, #DC_OP_CISW
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bl dcsw_op_level2
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/* ---------------------------------------------
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* Come out of intra cluster coherency
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* ---------------------------------------------
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*/
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pop {r12, lr}
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b cortex_a53_disable_smp
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endfunc cortex_a53_cluster_pwr_dwn
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#if REPORT_ERRATA
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/*
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* Errata printing function for Cortex A53. Must follow AAPCS.
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*/
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func cortex_a53_errata_report
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push {r12, lr}
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bl cpu_get_rev_var
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mov r4, r0
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/*
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* Report all errata. The revision-variant information is passed to
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* checking functions of each errata.
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*/
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report_errata ERRATA_A53_826319, cortex_a53, 826319
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report_errata ERRATA_A53_836870, cortex_a53, disable_non_temporal_hint
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report_errata ERRATA_A53_855873, cortex_a53, 855873
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pop {r12, lr}
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bx lr
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endfunc cortex_a53_errata_report
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#endif
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declare_cpu_ops cortex_a53, CORTEX_A53_MIDR, \
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cortex_a53_reset_func, \
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cortex_a53_core_pwr_dwn, \
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cortex_a53_cluster_pwr_dwn
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