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09d40e0e08
Enforce full include path for includes. Deprecate old paths.
The following folders inside include/lib have been left unchanged:
- include/lib/cpus/${ARCH}
- include/lib/el3_runtime/${ARCH}
The reason for this change is that having a global namespace for
includes isn't a good idea. It defeats one of the advantages of having
folders and it introduces problems that are sometimes subtle (because
you may not know the header you are actually including if there are two
of them).
For example, this patch had to be created because two headers were
called the same way: e0ea0928d5 ("Fix gpio includes of mt8173 platform
to avoid collision."). More recently, this patch has had similar
problems: 46f9b2c3a2 ("drivers: add tzc380 support").
This problem was introduced in commit 4ecca33988 ("Move include and
source files to logical locations"). At that time, there weren't too
many headers so it wasn't a real issue. However, time has shown that
this creates problems.
Platforms that want to preserve the way they include headers may add the
removed paths to PLAT_INCLUDES, but this is discouraged.
Change-Id: I39dc53ed98f9e297a5966e723d1936d6ccf2fc8f
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
160 lines
4.7 KiB
C
160 lines
4.7 KiB
C
/*
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* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef TZC380_H
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#define TZC380_H
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#include <drivers/arm/tzc_common.h>
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#include <lib/utils_def.h>
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#define TZC380_CONFIGURATION_OFF U(0x000)
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#define ACTION_OFF U(0x004)
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#define LOCKDOWN_RANGE_OFF U(0x008)
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#define LOCKDOWN_SELECT_OFF U(0x00C)
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#define INT_STATUS U(0x010)
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#define INT_CLEAR U(0x014)
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#define FAIL_ADDRESS_LOW_OFF U(0x020)
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#define FAIL_ADDRESS_HIGH_OFF U(0x024)
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#define FAIL_CONTROL_OFF U(0x028)
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#define FAIL_ID U(0x02c)
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#define SPECULATION_CTRL_OFF U(0x030)
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#define SECURITY_INV_EN_OFF U(0x034)
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#define REGION_SETUP_LOW_OFF(n) U(0x100 + (n) * 0x10)
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#define REGION_SETUP_HIGH_OFF(n) U(0x104 + (n) * 0x10)
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#define REGION_ATTRIBUTES_OFF(n) U(0x108 + (n) * 0x10)
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#define BUILD_CONFIG_AW_SHIFT 8
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#define BUILD_CONFIG_AW_MASK U(0x3f)
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#define BUILD_CONFIG_NR_SHIFT 0
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#define BUILD_CONFIG_NR_MASK U(0xf)
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#define ACTION_RV_SHIFT 0
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#define ACTION_RV_MASK U(0x3)
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#define ACTION_RV_LOWOK U(0x0)
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#define ACTION_RV_LOWERR U(0x1)
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#define ACTION_RV_HIGHOK U(0x2)
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#define ACTION_RV_HIGHERR U(0x3)
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/* Speculation is enabled by default. */
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#define SPECULATION_CTRL_WRITE_DISABLE BIT_32(1)
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#define SPECULATION_CTRL_READ_DISABLE BIT_32(0)
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#define INT_STATUS_OVERRUN_SHIFT 1
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#define INT_STATUS_OVERRUN_MASK U(0x1)
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#define INT_STATUS_STATUS_SHIFT 0
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#define INT_STATUS_STATUS_MASK U(0x1)
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#define INT_CLEAR_CLEAR_SHIFT 0
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#define INT_CLEAR_CLEAR_MASK U(0x1)
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#define TZC380_COMPONENT_ID U(0xb105f00d)
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#define TZC380_PERIPH_ID_LOW U(0x001bb380)
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#define TZC380_PERIPH_ID_HIGH U(0x00000004)
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#define TZC_SP_NS_W BIT_32(0)
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#define TZC_SP_NS_R BIT_32(1)
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#define TZC_SP_S_W BIT_32(2)
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#define TZC_SP_S_R BIT_32(3)
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#define TZC_ATTR_SP_SHIFT 28
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#define TZC_ATTR_SP_ALL ((TZC_SP_S_W | TZC_SP_S_R | TZC_SP_NS_W | \
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TZC_SP_NS_R) << TZC_ATTR_SP_SHIFT)
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#define TZC_ATTR_SP_S_RW ((TZC_SP_S_W | TZC_SP_S_R) << \
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TZC_ATTR_SP_SHIFT)
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#define TZC_ATTR_SP_NS_RW ((TZC_SP_NS_W | TZC_SP_NS_R) << \
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TZC_ATTR_SP_SHIFT)
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#define TZC_REGION_SIZE_32K U(0xe)
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#define TZC_REGION_SIZE_64K U(0xf)
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#define TZC_REGION_SIZE_128K U(0x10)
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#define TZC_REGION_SIZE_256K U(0x11)
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#define TZC_REGION_SIZE_512K U(0x12)
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#define TZC_REGION_SIZE_1M U(0x13)
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#define TZC_REGION_SIZE_2M U(0x14)
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#define TZC_REGION_SIZE_4M U(0x15)
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#define TZC_REGION_SIZE_8M U(0x16)
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#define TZC_REGION_SIZE_16M U(0x17)
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#define TZC_REGION_SIZE_32M U(0x18)
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#define TZC_REGION_SIZE_64M U(0x19)
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#define TZC_REGION_SIZE_128M U(0x1a)
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#define TZC_REGION_SIZE_256M U(0x1b)
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#define TZC_REGION_SIZE_512M U(0x1c)
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#define TZC_REGION_SIZE_1G U(0x1d)
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#define TZC_REGION_SIZE_2G U(0x1e)
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#define TZC_REGION_SIZE_4G U(0x1f)
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#define TZC_REGION_SIZE_8G U(0x20)
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#define TZC_REGION_SIZE_16G U(0x21)
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#define TZC_REGION_SIZE_32G U(0x22)
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#define TZC_REGION_SIZE_64G U(0x23)
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#define TZC_REGION_SIZE_128G U(0x24)
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#define TZC_REGION_SIZE_256G U(0x25)
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#define TZC_REGION_SIZE_512G U(0x26)
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#define TZC_REGION_SIZE_1T U(0x27)
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#define TZC_REGION_SIZE_2T U(0x28)
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#define TZC_REGION_SIZE_4T U(0x29)
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#define TZC_REGION_SIZE_8T U(0x2a)
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#define TZC_REGION_SIZE_16T U(0x2b)
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#define TZC_REGION_SIZE_32T U(0x2c)
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#define TZC_REGION_SIZE_64T U(0x2d)
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#define TZC_REGION_SIZE_128T U(0x2e)
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#define TZC_REGION_SIZE_256T U(0x2f)
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#define TZC_REGION_SIZE_512T U(0x30)
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#define TZC_REGION_SIZE_1P U(0x31)
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#define TZC_REGION_SIZE_2P U(0x32)
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#define TZC_REGION_SIZE_4P U(0x33)
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#define TZC_REGION_SIZE_8P U(0x34)
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#define TZC_REGION_SIZE_16P U(0x35)
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#define TZC_REGION_SIZE_32P U(0x36)
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#define TZC_REGION_SIZE_64P U(0x37)
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#define TZC_REGION_SIZE_128P U(0x38)
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#define TZC_REGION_SIZE_256P U(0x39)
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#define TZC_REGION_SIZE_512P U(0x3a)
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#define TZC_REGION_SIZE_1E U(0x3b)
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#define TZC_REGION_SIZE_2E U(0x3c)
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#define TZC_REGION_SIZE_4E U(0x3d)
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#define TZC_REGION_SIZE_8E U(0x3e)
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#define TZC_REGION_SIZE_16E U(0x3f)
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#define TZC_REGION_SIZE_SHIFT 0x1
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#define TZC_REGION_SIZE_MASK U(0x7e)
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#define TZC_ATTR_REGION_SIZE(s) ((s) << TZC_REGION_SIZE_SHIFT)
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#define TZC_ATTR_REGION_EN_SHIFT 0x0
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#define TZC_ATTR_REGION_EN_MASK U(0x1)
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#define TZC_ATTR_REGION_EN
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#define TZC_ATTR_REGION_ENABLE U(0x1)
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#define TZC_ATTR_REGION_DISABLE U(0x0)
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#define REGION_MAX 16
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void tzc380_init(uintptr_t base);
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void tzc380_configure_region(uint8_t region,
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uintptr_t region_base,
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unsigned int attr);
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void tzc380_set_action(tzc_action_t action);
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static inline void tzc_init(uintptr_t base)
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{
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tzc380_init(base);
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}
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static inline void tzc_configure_region(uint8_t region,
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uintptr_t region_base,
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unsigned int attr)
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{
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tzc380_configure_region(region, region_base, attr);
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}
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static inline void tzc_set_action(tzc_action_t action)
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{
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tzc380_set_action(action);
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}
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#endif /* TZC380_H */
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