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764c57f6f5
The PMC Scratch22 register contains the CPU reset vector to be used by the warmboot code to power up the CPU while resuming from system suspend. This patch locks this PMC register to avoid any further writes. Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
135 lines
4.5 KiB
C
135 lines
4.5 KiB
C
/*
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* Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <arch_helpers.h>
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#include <assert.h>
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#include <debug.h>
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#include <mmio.h>
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#include <pmc.h>
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#include <tegra_def.h>
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/* Module IDs used during power ungate procedure */
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static const int pmc_cpu_powergate_id[4] = {
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0, /* CPU 0 */
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9, /* CPU 1 */
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10, /* CPU 2 */
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11 /* CPU 3 */
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};
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/*******************************************************************************
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* Power ungate CPU to start the boot process. CPU reset vectors must be
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* populated before calling this function.
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******************************************************************************/
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void tegra_pmc_cpu_on(int cpu)
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{
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uint32_t val;
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/*
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* Check if CPU is already power ungated
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*/
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val = tegra_pmc_read_32(PMC_PWRGATE_STATUS);
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if (val & (1 << pmc_cpu_powergate_id[cpu]))
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return;
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/*
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* The PMC deasserts the START bit when it starts the power
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* ungate process. Loop till no power toggle is in progress.
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*/
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do {
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val = tegra_pmc_read_32(PMC_PWRGATE_TOGGLE);
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} while (val & PMC_TOGGLE_START);
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/*
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* Start the power ungate procedure
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*/
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val = pmc_cpu_powergate_id[cpu] | PMC_TOGGLE_START;
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tegra_pmc_write_32(PMC_PWRGATE_TOGGLE, val);
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/*
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* The PMC deasserts the START bit when it starts the power
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* ungate process. Loop till powergate START bit is asserted.
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*/
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do {
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val = tegra_pmc_read_32(PMC_PWRGATE_TOGGLE);
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} while (val & (1 << 8));
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/* loop till the CPU is power ungated */
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do {
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val = tegra_pmc_read_32(PMC_PWRGATE_STATUS);
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} while ((val & (1 << pmc_cpu_powergate_id[cpu])) == 0);
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}
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/*******************************************************************************
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* Setup CPU vectors for resume from deep sleep
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******************************************************************************/
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void tegra_pmc_cpu_setup(uint64_t reset_addr)
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{
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uint32_t val;
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tegra_pmc_write_32(PMC_SECURE_SCRATCH34, (reset_addr & 0xFFFFFFFF) | 1);
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val = reset_addr >> 32;
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tegra_pmc_write_32(PMC_SECURE_SCRATCH35, val & 0x7FF);
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}
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/*******************************************************************************
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* Lock CPU vectors to restrict further writes
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******************************************************************************/
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void tegra_pmc_lock_cpu_vectors(void)
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{
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uint32_t val;
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/* lock PMC_SECURE_SCRATCH22 */
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val = tegra_pmc_read_32(PMC_SECURE_DISABLE2);
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val |= PMC_SECURE_DISABLE2_WRITE22_ON;
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tegra_pmc_write_32(PMC_SECURE_DISABLE2, val);
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/* lock PMC_SECURE_SCRATCH34/35 */
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val = tegra_pmc_read_32(PMC_SECURE_DISABLE3);
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val |= (PMC_SECURE_DISABLE3_WRITE34_ON |
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PMC_SECURE_DISABLE3_WRITE35_ON);
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tegra_pmc_write_32(PMC_SECURE_DISABLE3, val);
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}
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/*******************************************************************************
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* Restart the system
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******************************************************************************/
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__dead2 void tegra_pmc_system_reset(void)
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{
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uint32_t reg;
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reg = tegra_pmc_read_32(PMC_CONFIG);
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reg |= 0x10; /* restart */
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tegra_pmc_write_32(PMC_CONFIG, reg);
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wfi();
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ERROR("Tegra System Reset: operation not handled.\n");
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panic();
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}
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