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6fa11a5e99
This patch fixes an issue in the cpu specific register reporting of FVP AEM model whereby crash reporting itself triggers an exception thus resulting in recursive crash prints. The input to the 'size_controlled_print' in the crash reporting framework should be a NULL terminated string. As there were no cpu specific register to be reported on FVP AEM model, the issue was caused by passing 0 instead of NULL terminated string to the above mentioned function. Change-Id: I664427b22b89977b389175dfde84c815f02c705a
97 lines
3.2 KiB
ArmAsm
97 lines
3.2 KiB
ArmAsm
/*
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* Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <aem_generic.h>
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#include <arch.h>
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#include <asm_macros.S>
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#include <cpu_macros.S>
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func aem_generic_core_pwr_dwn
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/* ---------------------------------------------
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* Disable the Data Cache.
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* ---------------------------------------------
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*/
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mrs x1, sctlr_el3
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bic x1, x1, #SCTLR_C_BIT
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msr sctlr_el3, x1
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isb
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mov x0, #DCCISW
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/* ---------------------------------------------
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* Flush L1 cache to PoU.
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* ---------------------------------------------
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*/
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b dcsw_op_louis
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endfunc aem_generic_core_pwr_dwn
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func aem_generic_cluster_pwr_dwn
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/* ---------------------------------------------
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* Disable the Data Cache.
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* ---------------------------------------------
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*/
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mrs x1, sctlr_el3
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bic x1, x1, #SCTLR_C_BIT
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msr sctlr_el3, x1
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isb
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/* ---------------------------------------------
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* Flush L1 and L2 caches to PoC.
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* ---------------------------------------------
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*/
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mov x0, #DCCISW
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b dcsw_op_all
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endfunc aem_generic_cluster_pwr_dwn
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/* ---------------------------------------------
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* This function provides cpu specific
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* register information for crash reporting.
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* It needs to return with x6 pointing to
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* a list of register names in ascii and
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* x8 - x15 having values of registers to be
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* reported.
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* ---------------------------------------------
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*/
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.section .rodata.aem_generic_regs, "aS"
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aem_generic_regs: /* The ascii list of register names to be reported */
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.asciz "" /* no registers to report */
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func aem_generic_cpu_reg_dump
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adr x6, aem_generic_regs
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ret
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endfunc aem_generic_cpu_reg_dump
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/* cpu_ops for Base AEM FVP */
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declare_cpu_ops aem_generic, BASE_AEM_MIDR, 1
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/* cpu_ops for Foundation FVP */
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declare_cpu_ops aem_generic, FOUNDATION_AEM_MIDR, 1
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