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https://github.com/ARM-software/arm-trusted-firmware.git
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95cfd4ad84
This patch extends the platform port by adding an API that returns
either the Root of Trust public key (ROTPK) or its hash. This is
usually stored in ROM or eFUSE memory. The ROTPK returned must be
encoded in DER format according to the following ASN.1 structure:
SubjectPublicKeyInfo ::= SEQUENCE {
algorithm AlgorithmIdentifier,
subjectPublicKey BIT STRING
}
In case the platform returns a hash of the key:
DigestInfo ::= SEQUENCE {
digestAlgorithm AlgorithmIdentifier,
keyDigest OCTET STRING
}
An implementation for ARM development platforms is provided in this
patch. When TBB is enabled, the ROTPK hash location must be specified
using the build option 'ARM_ROTPK_LOCATION'. Available options are:
- 'regs' : return the ROTPK hash stored in the Trusted
root-key storage registers.
- 'devel_rsa' : return a ROTPK hash embedded in the BL1 and
BL2 binaries. This hash has been obtained from the development
RSA public key located in 'plat/arm/board/common/rotpk'.
On FVP, the number of MMU tables has been increased to map and
access the ROTPK registers.
A new file 'board_common.mk' has been added to improve code sharing
in the ARM develelopment platforms.
Change-Id: Ib25862e5507d1438da10773e62bd338da8f360bf
98 lines
3.2 KiB
C
98 lines
3.2 KiB
C
/*
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* Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __SOC_CSS_DEF_H__
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#define __SOC_CSS_DEF_H__
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#include <common_def.h>
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#include <xlat_tables.h>
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/*
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* Definitions common to all ARM CSS SoCs
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*/
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/* Following covers ARM CSS SoC Peripherals and PCIe expansion area */
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#define SOC_CSS_DEVICE_BASE 0x40000000
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#define SOC_CSS_DEVICE_SIZE 0x40000000
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#define SOC_CSS_PCIE_CONTROL_BASE 0x7ff20000
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/* PL011 UART related constants */
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#define SOC_CSS_UART0_BASE 0x7ff80000
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#define SOC_CSS_UART1_BASE 0x7ff70000
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#define SOC_CSS_UART0_CLK_IN_HZ 7273800
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#define SOC_CSS_UART1_CLK_IN_HZ 7273800
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/* SoC NIC-400 Global Programmers View (GPV) */
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#define SOC_CSS_NIC400_BASE 0x7fd00000
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#define SOC_CSS_NIC400_USB_EHCI 0
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#define SOC_CSS_NIC400_TLX_MASTER 1
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#define SOC_CSS_NIC400_USB_OHCI 2
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#define SOC_CSS_NIC400_PL354_SMC 3
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/*
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* The apb4_bridge controls access to:
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* - the PCIe configuration registers
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* - the MMU units for USB, HDLCD and DMA
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*/
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#define SOC_CSS_NIC400_APB4_BRIDGE 4
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/* Keys */
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#define SOC_KEYS_BASE 0x7fe80000
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#define TZ_PUB_KEY_HASH_BASE (SOC_KEYS_BASE + 0x0000)
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#define TZ_PUB_KEY_HASH_SIZE 32
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#define HU_KEY_BASE (SOC_KEYS_BASE + 0x0020)
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#define HU_KEY_SIZE 16
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#define END_KEY_BASE (SOC_KEYS_BASE + 0x0044)
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#define END_KEY_SIZE 32
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#define SOC_CSS_MAP_DEVICE MAP_REGION_FLAT( \
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SOC_CSS_DEVICE_BASE, \
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SOC_CSS_DEVICE_SIZE, \
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MT_DEVICE | MT_RW | MT_SECURE)
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/*
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* The bootsec_bridge controls access to a bunch of peripherals, e.g. the UARTs.
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*/
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#define SOC_CSS_NIC400_BOOTSEC_BRIDGE 5
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#define SOC_CSS_NIC400_BOOTSEC_BRIDGE_UART1 (1 << 12)
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/*
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* Required platform porting definitions common to all ARM CSS SoCs
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*/
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/* 2MB used for SCP DDR retraining */
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#define PLAT_ARM_SCP_TZC_DRAM1_SIZE MAKE_ULL(0x00200000)
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#endif /* __SOC_CSS_DEF_H__ */
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