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edfda10a6b
This patch implements the TSP on Juno. It executes from on-chip Trusted SRAM. Also, the other bootloader images (i.e. BL1 R/W, BL2 and BL3-1) have been moved around. The reason is, although there was enough space overall to store the TSP in SRAM, there was no contiguous free chunk of SRAM big enough to hold it. This patch keeps the overall memory layout (i.e. keeping BL1 R/W at the bottom, BL2 at the top and BL3-1 in between) but moves the base addresses of all the bootloader images in such a way that: - memory fragmentation is reduced enough to fit BL3-2 in; - new base addresses are suitable for release builds as well as debug ones; - each image has a few extra kilobytes for future growth. BL3-1 and BL3-2 are the images which received the biggest allocations since they will most probably grow the most. This patch also adds instruction synchronization barriers around the code which handles the timer interrupt in the TSP. This ensures that the interrupt is not acknowledged after or EOIed before it is deactivated at the peripheral. Change-Id: I1c5b51858700027ee283ac85d18e06863a27c72e
113 lines
4.4 KiB
C
113 lines
4.4 KiB
C
/*
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* Copyright (c) 2014, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <arch_helpers.h>
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#include <assert.h>
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#include <platform.h>
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#include "tsp_private.h"
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/*******************************************************************************
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* Data structure to keep track of per-cpu secure generic timer context across
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* power management operations.
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******************************************************************************/
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typedef struct timer_context {
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uint64_t cval;
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uint32_t ctl;
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} timer_context_t;
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static timer_context_t pcpu_timer_context[PLATFORM_CORE_COUNT];
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/*******************************************************************************
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* This function initializes the generic timer to fire every 0.5 second
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******************************************************************************/
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void tsp_generic_timer_start(void)
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{
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uint64_t cval;
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uint32_t ctl = 0;
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/* The timer will fire every 0.5 second */
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cval = read_cntpct_el0() + (read_cntfrq_el0() >> 1);
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write_cntps_cval_el1(cval);
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/* Enable the secure physical timer */
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set_cntp_ctl_enable(ctl);
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write_cntps_ctl_el1(ctl);
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}
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/*******************************************************************************
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* This function deasserts the timer interrupt and sets it up again
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******************************************************************************/
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void tsp_generic_timer_handler(void)
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{
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/* Ensure that the timer did assert the interrupt */
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assert(get_cntp_ctl_istatus(read_cntps_ctl_el1()));
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/*
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* Disable the timer and reprogram it. The barriers ensure that there is
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* no reordering of instructions around the reprogramming code.
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*/
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isb();
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write_cntps_ctl_el1(0);
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tsp_generic_timer_start();
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isb();
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}
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/*******************************************************************************
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* This function deasserts the timer interrupt prior to cpu power down
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******************************************************************************/
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void tsp_generic_timer_stop(void)
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{
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/* Disable the timer */
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write_cntps_ctl_el1(0);
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}
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/*******************************************************************************
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* This function saves the timer context prior to cpu suspension
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******************************************************************************/
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void tsp_generic_timer_save(void)
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{
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uint32_t linear_id = platform_get_core_pos(read_mpidr());
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pcpu_timer_context[linear_id].cval = read_cntps_cval_el1();
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pcpu_timer_context[linear_id].ctl = read_cntps_ctl_el1();
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flush_dcache_range((uint64_t) &pcpu_timer_context[linear_id],
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sizeof(pcpu_timer_context[linear_id]));
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}
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/*******************************************************************************
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* This function restores the timer context post cpu resummption
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******************************************************************************/
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void tsp_generic_timer_restore(void)
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{
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uint32_t linear_id = platform_get_core_pos(read_mpidr());
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write_cntps_cval_el1(pcpu_timer_context[linear_id].cval);
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write_cntps_ctl_el1(pcpu_timer_context[linear_id].ctl);
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}
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