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a82ea1dbbf
The arm_fpga platform code contains an dubious line to initialise some timer. On closer inspection this turn out to be bogus, as this was only needed on some special (older) FPGA board, and is actually not needed on the current model. Also the base address was wrong anyways. Remove the code entirely. Change-Id: I02e71aea645051b5addb42d972d7a79f04b81106 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
41 lines
1.3 KiB
C
41 lines
1.3 KiB
C
/*
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* Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <lib/utils_def.h>
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#ifndef FPGA_DEF_H
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#define FPGA_DEF_H
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/*
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* These are set to large values to account for images describing systems with
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* larger cluster configurations.
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*
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* For cases where the number of clusters, cores or threads is smaller than a
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* maximum value below, this does not affect the PSCI functionality as any PEs
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* that are present will still be indexed appropriately regardless of any empty
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* entries in the array used to represent the topology.
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*/
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#define FPGA_MAX_CLUSTER_COUNT 2
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#define FPGA_MAX_CPUS_PER_CLUSTER 8
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#define FPGA_MAX_PE_PER_CPU 4
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#define FPGA_PRIMARY_CPU 0x0
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/*******************************************************************************
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* FPGA image memory map related constants
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******************************************************************************/
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/* UART base address and clock frequency, as configured by the image */
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#define PLAT_FPGA_BOOT_UART_BASE 0x7ff80000
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#define PLAT_FPGA_BOOT_UART_CLK_IN_HZ 10000000
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#define PLAT_FPGA_CRASH_UART_BASE PLAT_FPGA_BOOT_UART_BASE
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#define PLAT_FPGA_CRASH_UART_CLK_IN_HZ PLAT_FPGA_BOOT_UART_CLK_IN_HZ
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#define FPGA_TIMER_FREQUENCY 10000000
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#endif
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