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https://github.com/ARM-software/arm-trusted-firmware.git
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a82ea1dbbf
The arm_fpga platform code contains an dubious line to initialise some timer. On closer inspection this turn out to be bogus, as this was only needed on some special (older) FPGA board, and is actually not needed on the current model. Also the base address was wrong anyways. Remove the code entirely. Change-Id: I02e71aea645051b5addb42d972d7a79f04b81106 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
86 lines
1.9 KiB
C
86 lines
1.9 KiB
C
/*
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* Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <lib/mmio.h>
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#include <drivers/generic_delay_timer.h>
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#include <plat/common/platform.h>
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#include <platform_def.h>
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#include "fpga_private.h"
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static entry_point_info_t bl33_image_ep_info;
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uintptr_t plat_get_ns_image_entrypoint(void)
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{
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#ifdef PRELOADED_BL33_BASE
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return PRELOADED_BL33_BASE;
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#else
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return 0;
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#endif
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}
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uint32_t fpga_get_spsr_for_bl33_entry(void)
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{
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return SPSR_64(MODE_EL2, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS);
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}
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void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
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u_register_t arg2, u_register_t arg3)
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{
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fpga_console_init();
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bl33_image_ep_info.pc = plat_get_ns_image_entrypoint();
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bl33_image_ep_info.spsr = fpga_get_spsr_for_bl33_entry();
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SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE);
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/* Set x0-x3 for the primary CPU as expected by the kernel */
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bl33_image_ep_info.args.arg0 = (u_register_t)FPGA_PRELOADED_DTB_BASE;
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bl33_image_ep_info.args.arg1 = 0U;
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bl33_image_ep_info.args.arg2 = 0U;
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bl33_image_ep_info.args.arg3 = 0U;
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}
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void bl31_plat_arch_setup(void)
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{
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}
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void bl31_platform_setup(void)
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{
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/* Initialize the GIC driver, cpu and distributor interfaces */
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plat_fpga_gic_init();
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/* Write frequency to CNTCRL and initialize timer */
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generic_delay_timer_init();
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}
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entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
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{
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entry_point_info_t *next_image_info;
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next_image_info = &bl33_image_ep_info;
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/* Only expecting BL33: the kernel will run in EL2NS */
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assert(type == NON_SECURE);
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/* None of the images can have 0x0 as the entrypoint */
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if (next_image_info->pc) {
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return next_image_info;
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} else {
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return NULL;
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}
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}
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unsigned int plat_get_syscnt_freq2(void)
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{
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return FPGA_TIMER_FREQUENCY;
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}
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void bl31_plat_enable_mmu(uint32_t flags)
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{
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/* TODO: determine if MMU needs to be enabled */
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}
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