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https://github.com/ARM-software/arm-trusted-firmware.git
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82cb2c1ad9
To make software license auditing simpler, use SPDX[0] license identifiers instead of duplicating the license text in every file. NOTE: Files that have been imported by FreeBSD have not been modified. [0]: https://spdx.org/ Change-Id: I80a00e1f641b8cc075ca5a95b10607ed9ed8761a Signed-off-by: dp-arm <dimitris.papastamos@arm.com>
118 lines
2.9 KiB
ArmAsm
118 lines
2.9 KiB
ArmAsm
/*
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* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <assert_macros.S>
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#include <cortex_a53.h>
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#include <cpu_macros.S>
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#include <debug.h>
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/* ---------------------------------------------
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* Disable intra-cluster coherency
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* ---------------------------------------------
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*/
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func cortex_a53_disable_smp
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ldcopr16 r0, r1, CPUECTLR
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bic64_imm r0, r1, CPUECTLR_SMP_BIT
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stcopr16 r0, r1, CPUECTLR
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isb
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dsb sy
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bx lr
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endfunc cortex_a53_disable_smp
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/* -------------------------------------------------
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* The CPU Ops reset function for Cortex-A53.
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* -------------------------------------------------
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*/
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func cortex_a53_reset_func
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/* ---------------------------------------------
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* Enable the SMP bit.
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* ---------------------------------------------
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*/
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ldcopr16 r0, r1, CPUECTLR
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orr64_imm r0, r1, CPUECTLR_SMP_BIT
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stcopr16 r0, r1, CPUECTLR
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isb
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bx lr
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endfunc cortex_a53_reset_func
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/* ----------------------------------------------------
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* The CPU Ops core power down function for Cortex-A53.
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* ----------------------------------------------------
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*/
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func cortex_a53_core_pwr_dwn
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push {r12, lr}
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/* Assert if cache is enabled */
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#if ASM_ASSERTION
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ldcopr r0, SCTLR
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tst r0, #SCTLR_C_BIT
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ASM_ASSERT(eq)
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#endif
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/* ---------------------------------------------
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* Flush L1 caches.
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* ---------------------------------------------
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*/
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mov r0, #DC_OP_CISW
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bl dcsw_op_level1
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/* ---------------------------------------------
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* Come out of intra cluster coherency
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* ---------------------------------------------
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*/
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pop {r12, lr}
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b cortex_a53_disable_smp
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endfunc cortex_a53_core_pwr_dwn
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/* -------------------------------------------------------
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* The CPU Ops cluster power down function for Cortex-A53.
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* Clobbers: r0-r3
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* -------------------------------------------------------
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*/
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func cortex_a53_cluster_pwr_dwn
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push {r12, lr}
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/* Assert if cache is enabled */
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#if ASM_ASSERTION
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ldcopr r0, SCTLR
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tst r0, #SCTLR_C_BIT
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ASM_ASSERT(eq)
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#endif
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/* ---------------------------------------------
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* Flush L1 caches.
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* ---------------------------------------------
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*/
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mov r0, #DC_OP_CISW
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bl dcsw_op_level1
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/* ---------------------------------------------
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* Disable the optional ACP.
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* ---------------------------------------------
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*/
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bl plat_disable_acp
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/* ---------------------------------------------
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* Flush L2 caches.
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* ---------------------------------------------
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*/
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mov r0, #DC_OP_CISW
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bl dcsw_op_level2
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/* ---------------------------------------------
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* Come out of intra cluster coherency
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* ---------------------------------------------
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*/
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pop {r12, lr}
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b cortex_a53_disable_smp
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endfunc cortex_a53_cluster_pwr_dwn
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declare_cpu_ops cortex_a53, CORTEX_A53_MIDR, \
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cortex_a53_reset_func, \
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cortex_a53_core_pwr_dwn, \
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cortex_a53_cluster_pwr_dwn
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