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02446137a4
On a GICv2 system, interrupts that should be handled in the secure world are typically signalled as FIQs. On a GICv3 system, these interrupts are signalled as IRQs instead. The mechanism for handling both types of interrupts is the same in both cases. This patch enables the TSP to run on a GICv3 system by: 1. adding support for handling IRQs in the exception handling code. 2. removing use of "fiq" in the names of data structures, macros and functions. The build option TSPD_ROUTE_IRQ_TO_EL3 is deprecated and is replaced with a new build flag TSP_NS_INTR_ASYNC_PREEMPT. For compatibility reasons, if the former build flag is defined, it will be used to define the value for the new build flag. The documentation is also updated accordingly. Change-Id: I1807d371f41c3656322dd259340a57649833065e
251 lines
10 KiB
C
251 lines
10 KiB
C
/*
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* Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __TSPD_PRIVATE_H__
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#define __TSPD_PRIVATE_H__
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#include <arch.h>
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#include <context.h>
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#include <interrupt_mgmt.h>
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#include <platform_def.h>
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#include <psci.h>
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/*******************************************************************************
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* Secure Payload PM state information e.g. SP is suspended, uninitialised etc
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* and macros to access the state information in the per-cpu 'state' flags
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******************************************************************************/
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#define TSP_PSTATE_OFF 0
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#define TSP_PSTATE_ON 1
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#define TSP_PSTATE_SUSPEND 2
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#define TSP_PSTATE_SHIFT 0
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#define TSP_PSTATE_MASK 0x3
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#define get_tsp_pstate(state) ((state >> TSP_PSTATE_SHIFT) & TSP_PSTATE_MASK)
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#define clr_tsp_pstate(state) (state &= ~(TSP_PSTATE_MASK \
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<< TSP_PSTATE_SHIFT))
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#define set_tsp_pstate(st, pst) do { \
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clr_tsp_pstate(st); \
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st |= (pst & TSP_PSTATE_MASK) << \
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TSP_PSTATE_SHIFT; \
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} while (0);
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/*
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* This flag is used by the TSPD to determine if the TSP is servicing a standard
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* SMC request prior to programming the next entry into the TSP e.g. if TSP
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* execution is preempted by a non-secure interrupt and handed control to the
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* normal world. If another request which is distinct from what the TSP was
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* previously doing arrives, then this flag will be help the TSPD to either
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* reject the new request or service it while ensuring that the previous context
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* is not corrupted.
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*/
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#define STD_SMC_ACTIVE_FLAG_SHIFT 2
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#define STD_SMC_ACTIVE_FLAG_MASK 1
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#define get_std_smc_active_flag(state) ((state >> STD_SMC_ACTIVE_FLAG_SHIFT) \
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& STD_SMC_ACTIVE_FLAG_MASK)
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#define set_std_smc_active_flag(state) (state |= \
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1 << STD_SMC_ACTIVE_FLAG_SHIFT)
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#define clr_std_smc_active_flag(state) (state &= \
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~(STD_SMC_ACTIVE_FLAG_MASK \
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<< STD_SMC_ACTIVE_FLAG_SHIFT))
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/*******************************************************************************
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* Secure Payload execution state information i.e. aarch32 or aarch64
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******************************************************************************/
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#define TSP_AARCH32 MODE_RW_32
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#define TSP_AARCH64 MODE_RW_64
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/*******************************************************************************
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* The SPD should know the type of Secure Payload.
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******************************************************************************/
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#define TSP_TYPE_UP PSCI_TOS_NOT_UP_MIG_CAP
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#define TSP_TYPE_UPM PSCI_TOS_UP_MIG_CAP
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#define TSP_TYPE_MP PSCI_TOS_NOT_PRESENT_MP
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/*******************************************************************************
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* Secure Payload migrate type information as known to the SPD. We assume that
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* the SPD is dealing with an MP Secure Payload.
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******************************************************************************/
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#define TSP_MIGRATE_INFO TSP_TYPE_MP
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/*******************************************************************************
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* Number of cpus that the present on this platform. TODO: Rely on a topology
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* tree to determine this in the future to avoid assumptions about mpidr
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* allocation
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******************************************************************************/
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#define TSPD_CORE_COUNT PLATFORM_CORE_COUNT
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/*******************************************************************************
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* Constants that allow assembler code to preserve callee-saved registers of the
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* C runtime context while performing a security state switch.
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******************************************************************************/
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#define TSPD_C_RT_CTX_X19 0x0
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#define TSPD_C_RT_CTX_X20 0x8
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#define TSPD_C_RT_CTX_X21 0x10
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#define TSPD_C_RT_CTX_X22 0x18
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#define TSPD_C_RT_CTX_X23 0x20
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#define TSPD_C_RT_CTX_X24 0x28
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#define TSPD_C_RT_CTX_X25 0x30
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#define TSPD_C_RT_CTX_X26 0x38
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#define TSPD_C_RT_CTX_X27 0x40
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#define TSPD_C_RT_CTX_X28 0x48
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#define TSPD_C_RT_CTX_X29 0x50
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#define TSPD_C_RT_CTX_X30 0x58
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#define TSPD_C_RT_CTX_SIZE 0x60
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#define TSPD_C_RT_CTX_ENTRIES (TSPD_C_RT_CTX_SIZE >> DWORD_SHIFT)
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/*******************************************************************************
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* Constants that allow assembler code to preserve caller-saved registers of the
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* SP context while performing a TSP preemption.
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* Note: These offsets have to match with the offsets for the corresponding
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* registers in cpu_context as we are using memcpy to copy the values from
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* cpu_context to sp_ctx.
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******************************************************************************/
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#define TSPD_SP_CTX_X0 0x0
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#define TSPD_SP_CTX_X1 0x8
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#define TSPD_SP_CTX_X2 0x10
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#define TSPD_SP_CTX_X3 0x18
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#define TSPD_SP_CTX_X4 0x20
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#define TSPD_SP_CTX_X5 0x28
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#define TSPD_SP_CTX_X6 0x30
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#define TSPD_SP_CTX_X7 0x38
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#define TSPD_SP_CTX_X8 0x40
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#define TSPD_SP_CTX_X9 0x48
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#define TSPD_SP_CTX_X10 0x50
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#define TSPD_SP_CTX_X11 0x58
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#define TSPD_SP_CTX_X12 0x60
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#define TSPD_SP_CTX_X13 0x68
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#define TSPD_SP_CTX_X14 0x70
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#define TSPD_SP_CTX_X15 0x78
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#define TSPD_SP_CTX_X16 0x80
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#define TSPD_SP_CTX_X17 0x88
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#define TSPD_SP_CTX_SIZE 0x90
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#define TSPD_SP_CTX_ENTRIES (TSPD_SP_CTX_SIZE >> DWORD_SHIFT)
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#ifndef __ASSEMBLY__
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#include <cassert.h>
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#include <stdint.h>
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/*
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* The number of arguments to save during a SMC call for TSP.
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* Currently only x1 and x2 are used by TSP.
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*/
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#define TSP_NUM_ARGS 0x2
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/* AArch64 callee saved general purpose register context structure. */
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DEFINE_REG_STRUCT(c_rt_regs, TSPD_C_RT_CTX_ENTRIES);
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/*
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* Compile time assertion to ensure that both the compiler and linker
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* have the same double word aligned view of the size of the C runtime
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* register context.
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*/
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CASSERT(TSPD_C_RT_CTX_SIZE == sizeof(c_rt_regs_t), \
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assert_spd_c_rt_regs_size_mismatch);
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/* SEL1 Secure payload (SP) caller saved register context structure. */
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DEFINE_REG_STRUCT(sp_ctx_regs, TSPD_SP_CTX_ENTRIES);
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/*
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* Compile time assertion to ensure that both the compiler and linker
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* have the same double word aligned view of the size of the C runtime
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* register context.
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*/
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CASSERT(TSPD_SP_CTX_SIZE == sizeof(sp_ctx_regs_t), \
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assert_spd_sp_regs_size_mismatch);
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/*******************************************************************************
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* Structure which helps the SPD to maintain the per-cpu state of the SP.
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* 'saved_spsr_el3' - temporary copy to allow S-EL1 interrupt handling when
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* the TSP has been preempted.
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* 'saved_elr_el3' - temporary copy to allow S-EL1 interrupt handling when
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* the TSP has been preempted.
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* 'state' - collection of flags to track SP state e.g. on/off
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* 'mpidr' - mpidr to associate a context with a cpu
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* 'c_rt_ctx' - stack address to restore C runtime context from after
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* returning from a synchronous entry into the SP.
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* 'cpu_ctx' - space to maintain SP architectural state
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* 'saved_tsp_args' - space to store arguments for TSP arithmetic operations
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* which will queried using the TSP_GET_ARGS SMC by TSP.
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* 'sp_ctx' - space to save the SEL1 Secure Payload(SP) caller saved
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* register context after it has been preempted by an EL3
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* routed NS interrupt and when a Secure Interrupt is taken
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* to SP.
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******************************************************************************/
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typedef struct tsp_context {
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uint64_t saved_elr_el3;
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uint32_t saved_spsr_el3;
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uint32_t state;
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uint64_t mpidr;
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uint64_t c_rt_ctx;
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cpu_context_t cpu_ctx;
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uint64_t saved_tsp_args[TSP_NUM_ARGS];
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#if TSP_NS_INTR_ASYNC_PREEMPT
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sp_ctx_regs_t sp_ctx;
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#endif
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} tsp_context_t;
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/* Helper macros to store and retrieve tsp args from tsp_context */
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#define store_tsp_args(tsp_ctx, x1, x2) do {\
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tsp_ctx->saved_tsp_args[0] = x1;\
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tsp_ctx->saved_tsp_args[1] = x2;\
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} while (0)
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#define get_tsp_args(tsp_ctx, x1, x2) do {\
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x1 = tsp_ctx->saved_tsp_args[0];\
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x2 = tsp_ctx->saved_tsp_args[1];\
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} while (0)
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/* TSPD power management handlers */
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extern const spd_pm_ops_t tspd_pm;
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/*******************************************************************************
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* Forward declarations
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******************************************************************************/
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struct tsp_vectors;
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/*******************************************************************************
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* Function & Data prototypes
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******************************************************************************/
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uint64_t tspd_enter_sp(uint64_t *c_rt_ctx);
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void __dead2 tspd_exit_sp(uint64_t c_rt_ctx, uint64_t ret);
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uint64_t tspd_synchronous_sp_entry(tsp_context_t *tsp_ctx);
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void __dead2 tspd_synchronous_sp_exit(tsp_context_t *tsp_ctx, uint64_t ret);
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void tspd_init_tsp_ep_state(struct entry_point_info *tsp_ep,
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uint32_t rw,
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uint64_t pc,
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tsp_context_t *tsp_ctx);
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extern tsp_context_t tspd_sp_context[TSPD_CORE_COUNT];
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extern struct tsp_vectors *tsp_vectors;
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#endif /*__ASSEMBLY__*/
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#endif /* __TSPD_PRIVATE_H__ */
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