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02446137a4
On a GICv2 system, interrupts that should be handled in the secure world are typically signalled as FIQs. On a GICv3 system, these interrupts are signalled as IRQs instead. The mechanism for handling both types of interrupts is the same in both cases. This patch enables the TSP to run on a GICv3 system by: 1. adding support for handling IRQs in the exception handling code. 2. removing use of "fiq" in the names of data structures, macros and functions. The build option TSPD_ROUTE_IRQ_TO_EL3 is deprecated and is replaced with a new build flag TSP_NS_INTR_ASYNC_PREEMPT. For compatibility reasons, if the former build flag is defined, it will be used to define the value for the new build flag. The documentation is also updated accordingly. Change-Id: I1807d371f41c3656322dd259340a57649833065e
138 lines
4.5 KiB
C
138 lines
4.5 KiB
C
/*
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* Copyright (c) 2014, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __TSP_PRIVATE_H__
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#define __TSP_PRIVATE_H__
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/* Definitions to help the assembler access the SMC/ERET args structure */
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#define TSP_ARGS_SIZE 0x40
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#define TSP_ARG0 0x0
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#define TSP_ARG1 0x8
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#define TSP_ARG2 0x10
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#define TSP_ARG3 0x18
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#define TSP_ARG4 0x20
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#define TSP_ARG5 0x28
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#define TSP_ARG6 0x30
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#define TSP_ARG7 0x38
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#define TSP_ARGS_END 0x40
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#ifndef __ASSEMBLY__
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#include <cassert.h>
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#include <platform_def.h> /* For CACHE_WRITEBACK_GRANULE */
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#include <spinlock.h>
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#include <stdint.h>
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#include <tsp.h>
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typedef struct work_statistics {
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/* Number of s-el1 interrupts on this cpu */
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uint32_t sel1_intr_count;
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/* Number of non s-el1 interrupts on this cpu which preempted TSP */
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uint32_t preempt_intr_count;
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/* Number of sync s-el1 interrupts on this cpu */
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uint32_t sync_sel1_intr_count;
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/* Number of s-el1 interrupts returns on this cpu */
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uint32_t sync_sel1_intr_ret_count;
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uint32_t smc_count; /* Number of returns on this cpu */
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uint32_t eret_count; /* Number of entries on this cpu */
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uint32_t cpu_on_count; /* Number of cpu on requests */
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uint32_t cpu_off_count; /* Number of cpu off requests */
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uint32_t cpu_suspend_count; /* Number of cpu suspend requests */
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uint32_t cpu_resume_count; /* Number of cpu resume requests */
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} __aligned(CACHE_WRITEBACK_GRANULE) work_statistics_t;
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typedef struct tsp_args {
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uint64_t _regs[TSP_ARGS_END >> 3];
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} __aligned(CACHE_WRITEBACK_GRANULE) tsp_args_t;
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/* Macros to access members of the above structure using their offsets */
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#define read_sp_arg(args, offset) ((args)->_regs[offset >> 3])
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#define write_sp_arg(args, offset, val) (((args)->_regs[offset >> 3]) \
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= val)
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/*
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* Ensure that the assembler's view of the size of the tsp_args is the
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* same as the compilers
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*/
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CASSERT(TSP_ARGS_SIZE == sizeof(tsp_args_t), assert_sp_args_size_mismatch);
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void tsp_get_magic(uint64_t args[4]);
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tsp_args_t *tsp_cpu_resume_main(uint64_t arg0,
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uint64_t arg1,
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uint64_t arg2,
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uint64_t arg3,
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uint64_t arg4,
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uint64_t arg5,
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uint64_t arg6,
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uint64_t arg7);
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tsp_args_t *tsp_cpu_suspend_main(uint64_t arg0,
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uint64_t arg1,
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uint64_t arg2,
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uint64_t arg3,
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uint64_t arg4,
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uint64_t arg5,
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uint64_t arg6,
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uint64_t arg7);
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tsp_args_t *tsp_cpu_on_main(void);
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tsp_args_t *tsp_cpu_off_main(uint64_t arg0,
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uint64_t arg1,
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uint64_t arg2,
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uint64_t arg3,
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uint64_t arg4,
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uint64_t arg5,
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uint64_t arg6,
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uint64_t arg7);
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/* Generic Timer functions */
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void tsp_generic_timer_start(void);
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void tsp_generic_timer_handler(void);
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void tsp_generic_timer_stop(void);
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void tsp_generic_timer_save(void);
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void tsp_generic_timer_restore(void);
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/* S-EL1 interrupt management functions */
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void tsp_update_sync_sel1_intr_stats(uint32_t type, uint64_t elr_el3);
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/* Data structure to keep track of TSP statistics */
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extern spinlock_t console_lock;
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extern work_statistics_t tsp_stats[PLATFORM_CORE_COUNT];
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/* Vector table of jumps */
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extern tsp_vectors_t tsp_vector_table;
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#endif /* __ASSEMBLY__ */
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#endif /* __TSP_PRIVATE_H__ */
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