Arunachalam Ganapathy
a3ecbb3553
plat: tc0: Add TZC DRAM1 region for SPMC and trusted OS
...
- Reserve 32MB below ARM_AP_TZC_DRAM1_BASE for TC0_TZC_DRAM1
- Add TC0_NS_DRAM1 base and mapping
- Reserve memory region in tc0.dts
Change-Id: If2431f7f68e4255e28c86a0e89637dab7c424a13
Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
2020-10-20 20:07:06 +00:00
..
2020-04-17 21:12:15 +01:00
2020-09-29 13:28:25 +01:00
2020-09-07 13:13:04 +01:00
2020-07-06 16:55:43 +01:00
2020-07-06 16:55:43 +01:00
2020-08-28 09:50:25 +00:00
2020-05-19 13:16:22 +00:00
2020-05-19 13:16:22 +00:00
2020-05-19 13:16:22 +00:00
2020-05-19 13:16:22 +00:00
2020-05-19 13:16:22 +00:00
2020-05-19 13:16:22 +00:00
2020-06-09 19:01:14 +00:00
2020-05-19 13:16:22 +00:00
2020-05-19 13:16:22 +00:00
2020-05-19 13:16:22 +00:00
2020-05-19 13:16:22 +00:00
2020-05-19 13:16:22 +00:00
2020-05-19 13:16:22 +00:00
2020-05-19 13:16:22 +00:00
2020-05-19 13:16:22 +00:00
2018-04-24 08:30:01 +01:00
2020-01-14 10:30:38 +01:00
2020-01-14 10:30:38 +01:00
2020-10-08 18:39:55 +05:30
2020-09-28 19:33:24 +05:30
2020-09-16 22:01:00 +05:30
2020-07-30 18:44:54 +05:30
2020-07-30 18:44:54 +05:30
2020-07-30 15:56:13 +00:00
2018-04-24 08:30:01 +01:00
2018-04-24 08:30:01 +01:00
2020-09-24 09:07:57 +02:00
2020-09-24 09:07:57 +02:00
2019-04-26 19:17:17 +05:30
2020-09-24 09:07:57 +02:00
2020-09-24 09:07:57 +02:00
2020-09-24 09:07:57 +02:00
2020-09-24 09:07:57 +02:00
2020-09-24 09:07:57 +02:00
2020-09-24 09:07:57 +02:00
2020-09-24 09:07:57 +02:00
2020-10-12 14:46:07 +02:00
2020-09-24 09:07:57 +02:00
2020-09-24 09:07:57 +02:00
2020-09-24 09:07:57 +02:00
2020-09-24 09:07:57 +02:00
2020-09-24 09:07:57 +02:00
2020-10-13 18:05:23 +02:00
2020-10-12 14:46:07 +02:00
2020-10-20 20:07:06 +00:00