Arunachalam Ganapathy a3ecbb3553 plat: tc0: Add TZC DRAM1 region for SPMC and trusted OS
- Reserve 32MB below ARM_AP_TZC_DRAM1_BASE for TC0_TZC_DRAM1
- Add TC0_NS_DRAM1 base and mapping
- Reserve memory region in tc0.dts

Change-Id: If2431f7f68e4255e28c86a0e89637dab7c424a13
Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
2020-10-20 20:07:06 +00:00
..
2020-09-29 13:28:25 +01:00
2018-04-24 08:30:01 +01:00