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https://github.com/ARM-software/arm-trusted-firmware.git
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1d333e6909
New SoC is a78 based with gicv3 and uart over pl011. Communication interfaces are similar to Versal platform. System starts with Xilinx PLM firmware which loads TF-A(bl31) to DDR, which is already configured, and jumps to it. PLM also prepare handoff structure for TF-A with information what components were load and flags which indicate which EL level SW should be started. Signed-off-by: Michal Simek <michal.simek@amd.com> Signed-off-by: Akshay Belsare <Akshay.Belsare@amd.com> Change-Id: I2a16c242a77be6c91be3d198727dc3b9bbb97410
111 lines
3.3 KiB
ArmAsm
111 lines
3.3 KiB
ArmAsm
/*
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* Copyright (c) 2018-2021, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2018-2022, Xilinx, Inc. All rights reserved.
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* Copyright (C) 2022, Advanced Micro Devices, Inc. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <drivers/arm/gicv3.h>
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#include <platform_def.h>
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.globl plat_secondary_cold_boot_setup
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.globl plat_is_my_cpu_primary
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.globl platform_mem_init
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.globl plat_my_core_pos
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.globl plat_crash_console_init
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.globl plat_crash_console_putc
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.globl plat_crash_console_flush
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/* -----------------------------------------------------
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* void plat_secondary_cold_boot_setup (void);
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*
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* This function performs any platform specific actions
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* needed for a secondary cpu after a cold reset e.g
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* mark the cpu's presence, mechanism to place it in a
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* holding pen etc.
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* TODO: Should we read the PSYS register to make sure
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* that the request has gone through.
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* -----------------------------------------------------
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*/
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func plat_secondary_cold_boot_setup
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mrs x0, mpidr_el1
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/*
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* There is no sane reason to come out of this wfi. This
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* cpu will be powered on and reset by the cpu_on pm api
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*/
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dsb sy
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bl plat_panic_handler
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endfunc plat_secondary_cold_boot_setup
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func plat_is_my_cpu_primary
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mov x9, x30
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bl plat_my_core_pos
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cmp x0, #VERSAL_NET_PRIMARY_CPU
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cset x0, eq
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ret x9
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endfunc plat_is_my_cpu_primary
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/* -----------------------------------------------------
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* unsigned int plat_my_core_pos(void)
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* This function uses the plat_core_pos_by_mpidr()
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* definition to get the index of the calling CPU.
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* -----------------------------------------------------
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*/
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func plat_my_core_pos
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mrs x0, mpidr_el1
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b plat_core_pos_by_mpidr
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endfunc plat_my_core_pos
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/* ---------------------------------------------------------------------
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* We don't need to carry out any memory initialization on Versal NET
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* platform. The Secure RAM is accessible straight away.
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* ---------------------------------------------------------------------
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*/
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func platform_mem_init
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ret
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endfunc platform_mem_init
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/* ---------------------------------------------
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* int plat_crash_console_init(void)
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* Function to initialize the crash console
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* without a C Runtime to print crash report.
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* Clobber list : x0, x1, x2
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* ---------------------------------------------
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*/
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func plat_crash_console_init
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/* mov_imm x0, PLAT_VERSAL_NET_CRASH_UART_BASE
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mov_imm x1, PLAT_VERSAL_NET_CRASH_UART_CLK_IN_HZ
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mov_imm x2, VERSAL_NET_CONSOLE_BAUDRATE
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b console_pl011_core_init */
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endfunc plat_crash_console_init
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/* ---------------------------------------------
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* int plat_crash_console_putc(int c)
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* Function to print a character on the crash
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* console without a C Runtime.
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* Clobber list : x1, x2
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* ---------------------------------------------
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*/
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func plat_crash_console_putc
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mov_imm x1, PLAT_VERSAL_NET_CRASH_UART_BASE
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b console_pl011_core_putc
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endfunc plat_crash_console_putc
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/* ---------------------------------------------
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* void plat_crash_console_flush()
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* Function to force a write of all buffered
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* data that hasn't been output.
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* Out : void.
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* Clobber list : x0, x1
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* ---------------------------------------------
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*/
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func plat_crash_console_flush
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mov_imm x0, PLAT_VERSAL_NET_CRASH_UART_BASE
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b console_pl011_core_flush
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endfunc plat_crash_console_flush
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