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e497421d7f
Only one hardcode interrupt handler is supported as of now. This is IPI interrupt between APU and PMC processor. This patch adds infrastructure to register multiple interrupt handlers. This infrastructure was used and tested for two interrupts and so, interrupt id and handler container size is 2 which is defined by MAX_INTR_EL3. Interrupt id is not used as container index due to size constraints. User is expected to adjust MAX_INTR_EL3 based on how many interrupts are handled in TF-A Signed-off-by: Tanmay Shah <tanmay.shah@amd.com> Change-Id: Id49d94f6773fbb6874ccf89c0d12572efc7e678e
40 lines
1.1 KiB
C
40 lines
1.1 KiB
C
/*
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* Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2018-2022, Xilinx, Inc. All rights reserved.
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* Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef PLAT_PRIVATE_H
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#define PLAT_PRIVATE_H
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#include <lib/xlat_tables/xlat_tables.h>
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#include <bl31/interrupt_mgmt.h>
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typedef struct versal_intr_info_type_el3 {
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uint32_t id;
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interrupt_type_handler_t handler;
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} versal_intr_info_type_el3_t;
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void versal_config_setup(void);
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const mmap_region_t *plat_versal_get_mmap(void);
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void plat_versal_gic_driver_init(void);
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void plat_versal_gic_init(void);
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void plat_versal_gic_cpuif_enable(void);
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void plat_versal_gic_cpuif_disable(void);
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void plat_versal_gic_pcpu_init(void);
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void plat_versal_gic_save(void);
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void plat_versal_gic_resume(void);
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uint32_t versal_calc_core_pos(u_register_t mpidr);
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/*
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* Register handler to specific GIC entrance
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* for INTR_TYPE_EL3 type of interrupt
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*/
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int32_t request_intr_type_el3(uint32_t irq, interrupt_type_handler_t fiq_handler);
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#endif /* PLAT_PRIVATE_H */
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