mirror of
https://github.com/ARM-software/arm-trusted-firmware.git
synced 2025-08-14 08:27:00 +02:00
f55ef85ebf
So far the px30-related ddr security was loading data for regions to secure from a pre-specified memory location and also setting region0 to secure the first megabyte of memory in hard-coded setting (top=0, end=0, meaning 1MB). To make things more explicit and easier to read add a function doing the settings for specified memory areas, like other socs have and also add an assert to make sure any descriptor read from memory does not overlap the TZRAM security in region0 and TEE security in region1. Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com> Change-Id: I78441875112bf66a62fde5f1789f4e52a78ef95f
177 lines
4.5 KiB
C
177 lines
4.5 KiB
C
/*
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* Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef __PX30_DEF_H__
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#define __PX30_DEF_H__
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#define MAJOR_VERSION (1)
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#define MINOR_VERSION (0)
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#define SIZE_K(n) ((n) * 1024)
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#define SIZE_M(n) ((n) * 1024 * 1024)
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#define WITH_16BITS_WMSK(bits) (0xffff0000 | (bits))
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/* Special value used to verify platform parameters from BL2 to BL3-1 */
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#define RK_BL31_PLAT_PARAM_VAL 0x0f1e2d3c4b5a6978ULL
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#define PMU_BASE 0xff000000
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#define PMU_SIZE SIZE_K(64)
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#define PMUGRF_BASE 0xff010000
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#define PMUGRF_SIZE SIZE_K(64)
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#define PMUSRAM_BASE 0xff020000
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#define PMUSRAM_SIZE SIZE_K(64)
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#define PMUSRAM_RSIZE SIZE_K(8)
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#define UART0_BASE 0xff030000
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#define UART0_SIZE SIZE_K(64)
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#define GPIO0_BASE 0xff040000
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#define GPIO0_SIZE SIZE_K(64)
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#define PMUSGRF_BASE 0xff050000
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#define PMUSGRF_SIZE SIZE_K(64)
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#define INTSRAM_BASE 0xff0e0000
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#define INTSRAM_SIZE SIZE_K(64)
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#define SGRF_BASE 0xff11c000
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#define SGRF_SIZE SIZE_K(16)
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#define GIC400_BASE 0xff130000
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#define GIC400_SIZE SIZE_K(64)
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#define GRF_BASE 0xff140000
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#define GRF_SIZE SIZE_K(64)
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#define UART1_BASE 0xff158000
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#define UART1_SIZE SIZE_K(64)
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#define UART2_BASE 0xff160000
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#define UART2_SIZE SIZE_K(64)
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#define UART3_BASE 0xff168000
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#define UART3_SIZE SIZE_K(64)
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#define UART5_BASE 0xff178000
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#define UART5_SIZE SIZE_K(64)
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#define I2C0_BASE 0xff180000
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#define I2C0_SIZE SIZE_K(64)
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#define PWM0_BASE 0xff200000
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#define PWM0_SIZE SIZE_K(32)
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#define PWM1_BASE 0xff208000
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#define PWM1_SIZE SIZE_K(32)
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#define NTIME_BASE 0xff210000
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#define NTIME_SIZE SIZE_K(64)
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#define STIME_BASE 0xff220000
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#define STIME_SIZE SIZE_K(64)
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#define DCF_BASE 0xff230000
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#define DCF_SIZE SIZE_K(64)
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#define GPIO1_BASE 0xff250000
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#define GPIO1_SIZE SIZE_K(64)
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#define GPIO2_BASE 0xff260000
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#define GPIO2_SIZE SIZE_K(64)
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#define GPIO3_BASE 0xff270000
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#define GPIO3_SIZE SIZE_K(64)
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#define DDR_PHY_BASE 0xff2a0000
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#define DDR_PHY_SIZE SIZE_K(64)
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#define CRU_BASE 0xff2b0000
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#define CRU_SIZE SIZE_K(32)
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#define CRU_BOOST_BASE 0xff2b8000
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#define CRU_BOOST_SIZE SIZE_K(16)
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#define PMUCRU_BASE 0xff2bc000
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#define PMUCRU_SIZE SIZE_K(16)
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#define VOP_BASE 0xff460000
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#define VOP_SIZE SIZE_K(16)
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#define SERVER_MSCH_BASE 0xff530000
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#define SERVER_MSCH_SIZE SIZE_K(64)
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#define FIREWALL_DDR_BASE 0xff534000
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#define FIREWALL_DDR_SIZE SIZE_K(16)
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#define DDR_UPCTL_BASE 0xff600000
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#define DDR_UPCTL_SIZE SIZE_K(64)
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#define DDR_MNTR_BASE 0xff610000
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#define DDR_MNTR_SIZE SIZE_K(64)
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#define DDR_STDBY_BASE 0xff620000
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#define DDR_STDBY_SIZE SIZE_K(64)
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#define DDRGRF_BASE 0xff630000
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#define DDRGRF_SIZE SIZE_K(32)
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/**************************************************************************
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* UART related constants
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**************************************************************************/
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#define PX30_UART_BASE UART2_BASE
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#define PX30_BAUDRATE 1500000
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#define PX30_UART_CLOCK 24000000
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/******************************************************************************
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* System counter frequency related constants
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******************************************************************************/
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#define SYS_COUNTER_FREQ_IN_TICKS 24000000
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#define SYS_COUNTER_FREQ_IN_MHZ 24
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/******************************************************************************
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* GIC-400 & interrupt handling related constants
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******************************************************************************/
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/* Base rk_platform compatible GIC memory map */
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#define PX30_GICD_BASE (GIC400_BASE + 0x1000)
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#define PX30_GICC_BASE (GIC400_BASE + 0x2000)
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#define PX30_GICR_BASE 0 /* no GICR in GIC-400 */
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/******************************************************************************
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* sgi, ppi
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******************************************************************************/
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#define RK_IRQ_SEC_PHY_TIMER 29
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#define RK_IRQ_SEC_SGI_0 8
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#define RK_IRQ_SEC_SGI_1 9
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#define RK_IRQ_SEC_SGI_2 10
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#define RK_IRQ_SEC_SGI_3 11
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#define RK_IRQ_SEC_SGI_4 12
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#define RK_IRQ_SEC_SGI_5 13
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#define RK_IRQ_SEC_SGI_6 14
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#define RK_IRQ_SEC_SGI_7 15
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/*
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* Define a list of Group 0 interrupts.
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*/
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#define PLAT_RK_GICV2_G0_IRQS \
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INTR_PROP_DESC(RK_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, \
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GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL), \
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INTR_PROP_DESC(RK_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, \
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GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL)
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#define SHARE_MEM_BASE 0x100000/* [1MB, 1MB+60K]*/
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#define SHARE_MEM_PAGE_NUM 15
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#define SHARE_MEM_SIZE SIZE_K(SHARE_MEM_PAGE_NUM * 4)
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#define DDR_PARAM_BASE 0x02000000
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#define DDR_PARAM_SIZE SIZE_K(4)
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#endif /* __PLAT_DEF_H__ */
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