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df5a968317
Transfering the regions of ddr memory to additionally protect is very much
specific to some rockchip internal first stage bootloader and doesn't get
used in either mainline uboot or even Rockchip's published vendor uboot
sources.
This results in a big error
ERROR: over or zero region, nr=0, max=10
getting emitted on every boot for most users and such a message coming
from early firmware might actually confuse developers working with the
system.
As this mechanism seems to be only be used by Rockchip's internal miniloader
hide it behind a build conditional, so it doesn't confuse people too much.
Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Change-Id: I52c02decc60fd431ea78c7486cad5bac82bdbfbe
104 lines
2.9 KiB
C
104 lines
2.9 KiB
C
/*
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* Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <ddr_parameter.h>
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#include <plat_private.h>
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#include <secure.h>
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#include <px30_def.h>
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/**
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* There are 8 regions for DDR security control
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* @rgn - the DDR regions 0 ~ 7 which are can be configured.
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* @st - start address to set as secure
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* @sz - length of area to set as secure
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* The internal unit is megabytes, so memory areas need to be aligned
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* to megabyte borders.
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*/
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static void secure_ddr_region(uint32_t rgn,
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uintptr_t st, size_t sz)
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{
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uintptr_t ed = st + sz;
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uintptr_t st_mb, ed_mb;
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uint32_t val;
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assert(rgn <= 7);
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assert(st < ed);
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/* check aligned 1MB */
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assert(st % SIZE_M(1) == 0);
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assert(ed % SIZE_M(1) == 0);
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st_mb = st / SIZE_M(1);
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ed_mb = ed / SIZE_M(1);
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/* map top and base */
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mmio_write_32(FIREWALL_DDR_BASE +
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FIREWALL_DDR_FW_DDR_RGN(rgn),
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RG_MAP_SECURE(ed_mb, st_mb));
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/* enable secure */
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val = mmio_read_32(FIREWALL_DDR_BASE + FIREWALL_DDR_FW_DDR_CON_REG);
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val |= BIT(rgn);
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mmio_write_32(FIREWALL_DDR_BASE +
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FIREWALL_DDR_FW_DDR_CON_REG, val);
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}
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void secure_timer_init(void)
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{
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mmio_write_32(STIMER_CHN_BASE(1) + TIMER_CONTROL_REG,
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TIMER_DIS);
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mmio_write_32(STIMER_CHN_BASE(1) + TIMER_LOAD_COUNT0, 0xffffffff);
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mmio_write_32(STIMER_CHN_BASE(1) + TIMER_LOAD_COUNT1, 0xffffffff);
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/* auto reload & enable the timer */
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mmio_write_32(STIMER_CHN_BASE(1) + TIMER_CONTROL_REG,
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TIMER_EN | TIMER_FMODE);
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}
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void sgrf_init(void)
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{
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#ifdef PLAT_RK_SECURE_DDR_MINILOADER
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uint32_t i;
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struct param_ddr_usage usg;
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/* general secure regions */
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usg = ddr_region_usage_parse(DDR_PARAM_BASE,
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PLAT_MAX_DDR_CAPACITY_MB);
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/* region-0 for TF-A, region-1 for optional OP-TEE */
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assert(usg.s_nr < 7);
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for (i = 0; i < usg.s_nr; i++)
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secure_ddr_region(7 - i, usg.s_top[i], usg.s_base[i]);
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#endif
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/* secure the trustzone ram */
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secure_ddr_region(0, TZRAM_BASE, TZRAM_SIZE);
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/* set all slave ip into no-secure, except stimer */
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mmio_write_32(SGRF_BASE + SGRF_SOC_CON(4), SGRF_SLV_S_ALL_NS);
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mmio_write_32(SGRF_BASE + SGRF_SOC_CON(5), SGRF_SLV_S_ALL_NS);
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mmio_write_32(SGRF_BASE + SGRF_SOC_CON(6), SGRF_SLV_S_ALL_NS);
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mmio_write_32(SGRF_BASE + SGRF_SOC_CON(7), SGRF_SLV_S_ALL_NS);
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mmio_write_32(SGRF_BASE + SGRF_SOC_CON(8), 0x00030000);
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/* set master crypto to no-secure, dcf to secure */
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mmio_write_32(SGRF_BASE + SGRF_SOC_CON(3), 0x000f0003);
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/* set DMAC into no-secure */
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mmio_write_32(SGRF_BASE + SGRF_DMAC_CON(0), DMA_IRQ_BOOT_NS);
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mmio_write_32(SGRF_BASE + SGRF_DMAC_CON(1), DMA_PERI_CH_NS_15_0);
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mmio_write_32(SGRF_BASE + SGRF_DMAC_CON(2), DMA_PERI_CH_NS_19_16);
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mmio_write_32(SGRF_BASE + SGRF_DMAC_CON(3), DMA_MANAGER_BOOT_NS);
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/* soft reset dma before use */
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mmio_write_32(SGRF_BASE + SGRF_SOC_CON(1), DMA_SOFTRST_REQ);
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udelay(5);
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mmio_write_32(SGRF_BASE + SGRF_SOC_CON(1), DMA_SOFTRST_RLS);
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}
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