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09d40e0e08
Enforce full include path for includes. Deprecate old paths.
The following folders inside include/lib have been left unchanged:
- include/lib/cpus/${ARCH}
- include/lib/el3_runtime/${ARCH}
The reason for this change is that having a global namespace for
includes isn't a good idea. It defeats one of the advantages of having
folders and it introduces problems that are sometimes subtle (because
you may not know the header you are actually including if there are two
of them).
For example, this patch had to be created because two headers were
called the same way: e0ea0928d5 ("Fix gpio includes of mt8173 platform
to avoid collision."). More recently, this patch has had similar
problems: 46f9b2c3a2 ("drivers: add tzc380 support").
This problem was introduced in commit 4ecca33988 ("Move include and
source files to logical locations"). At that time, there weren't too
many headers so it wasn't a real issue. However, time has shown that
this creates problems.
Platforms that want to preserve the way they include headers may add the
removed paths to PLAT_INCLUDES, but this is discouraged.
Change-Id: I39dc53ed98f9e297a5966e723d1936d6ccf2fc8f
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
96 lines
3.1 KiB
C
96 lines
3.1 KiB
C
/*
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* Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <platform_def.h>
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#include <common/bl_common.h>
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#include <common/interrupt_props.h>
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#include <drivers/arm/gicv3.h>
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#include <lib/utils.h>
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#include <plat/common/platform.h>
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/******************************************************************************
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* The following functions are defined as weak to allow a platform to override
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* the way the GICv3 driver is initialised and used.
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*****************************************************************************/
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#pragma weak plat_rockchip_gic_driver_init
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#pragma weak plat_rockchip_gic_init
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#pragma weak plat_rockchip_gic_cpuif_enable
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#pragma weak plat_rockchip_gic_cpuif_disable
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#pragma weak plat_rockchip_gic_pcpu_init
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/* The GICv3 driver only needs to be initialized in EL3 */
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uintptr_t rdistif_base_addrs[PLATFORM_CORE_COUNT];
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static const interrupt_prop_t g01s_interrupt_props[] = {
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PLAT_RK_GICV3_G0_IRQS,
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PLAT_RK_GICV3_G1S_IRQS
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};
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static unsigned int plat_rockchip_mpidr_to_core_pos(unsigned long mpidr)
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{
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return (unsigned int)plat_core_pos_by_mpidr(mpidr);
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}
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const gicv3_driver_data_t rockchip_gic_data = {
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.gicd_base = PLAT_RK_GICD_BASE,
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.gicr_base = PLAT_RK_GICR_BASE,
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.interrupt_props = g01s_interrupt_props,
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.interrupt_props_num = ARRAY_SIZE(g01s_interrupt_props),
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.rdistif_num = PLATFORM_CORE_COUNT,
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.rdistif_base_addrs = rdistif_base_addrs,
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.mpidr_to_core_pos = plat_rockchip_mpidr_to_core_pos,
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};
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void plat_rockchip_gic_driver_init(void)
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{
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/*
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* The GICv3 driver is initialized in EL3 and does not need
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* to be initialized again in SEL1. This is because the S-EL1
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* can use GIC system registers to manage interrupts and does
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* not need GIC interface base addresses to be configured.
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*/
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#ifdef IMAGE_BL31
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gicv3_driver_init(&rockchip_gic_data);
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#endif
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}
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/******************************************************************************
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* RockChip common helper to initialize the GIC. Only invoked
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* by BL31
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*****************************************************************************/
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void plat_rockchip_gic_init(void)
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{
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gicv3_distif_init();
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gicv3_rdistif_init(plat_my_core_pos());
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gicv3_cpuif_enable(plat_my_core_pos());
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}
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/******************************************************************************
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* RockChip common helper to enable the GIC CPU interface
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*****************************************************************************/
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void plat_rockchip_gic_cpuif_enable(void)
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{
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gicv3_cpuif_enable(plat_my_core_pos());
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}
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/******************************************************************************
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* RockChip common helper to disable the GIC CPU interface
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*****************************************************************************/
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void plat_rockchip_gic_cpuif_disable(void)
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{
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gicv3_cpuif_disable(plat_my_core_pos());
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}
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/******************************************************************************
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* RockChip common helper to initialize the per-cpu redistributor interface
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* in GICv3
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*****************************************************************************/
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void plat_rockchip_gic_pcpu_init(void)
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{
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gicv3_rdistif_init(plat_my_core_pos());
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}
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