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82e18f8998
There are a number or ARMv7 Rockchip SoCs that are very similar in their bringup routines to the existing arm64 SoCs, so there is quite a high commonality possible here. Things like virtualization also need psci and hyp-mode and instead of trying to cram this into bootloaders like u-boot, barebox or coreboot (all used in the field), re-use the existing infrastructure in TF-A for this (both Rockchip plat support and armv7 support in general). So add core support for aarch32 Rockchip SoCs, with actual soc support following in a separate patch. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Change-Id: I298453985b5d8434934fc0c742fda719e994ba0b
57 lines
1003 B
ArmAsm
57 lines
1003 B
ArmAsm
/*
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* Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <platform_def.h>
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.globl pmu_cpuson_entrypoint
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.macro pmusram_entry_func _name
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.section .pmusram.entry, "ax"
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.type \_name, %function
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.cfi_startproc
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\_name:
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.endm
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pmusram_entry_func pmu_cpuson_entrypoint
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#if PSRAM_CHECK_WAKEUP_CPU
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check_wake_cpus:
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ldcopr r0, MPIDR
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and r1, r0, #MPIDR_CPU_MASK
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#ifdef PLAT_RK_MPIDR_CLUSTER_MASK
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and r0, r0, #PLAT_RK_MPIDR_CLUSTER_MASK
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#else
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and r0, r0, #MPIDR_CLUSTER_MASK
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#endif
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orr r0, r0, r1
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/* primary_cpu */
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ldr r1, boot_mpidr
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cmp r0, r1
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beq sys_wakeup
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/*
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* If the core is not the primary cpu,
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* force the core into wfe.
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*/
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wfe_loop:
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wfe
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b wfe_loop
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sys_wakeup:
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#endif
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#if PSRAM_DO_DDR_RESUME
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ddr_resume:
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ldr r2, =__bl32_sram_stack_end
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mov sp, r2
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bl dmc_resume
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#endif
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bl sram_restore
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sys_resume:
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bl sp_min_warm_entrypoint
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endfunc pmu_cpuson_entrypoint
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