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af6447315c
Booting e.g. Linux in the non-secure world does not work with the
msm8916 port yet because essential hardware is not made available to
the non-secure world. Add more platform initialization to:
- Initialize the GICv2 and mark secure interrupts.
Only secure SGIs/PPIs so far. Override the GICD_PIDR2_GICV2
register address in platform_def.h to avoid a failing assert()
because of a (hardware) mistake in Qualcomm's GICv2 implementation.
- Make a timer frame available to the non-secure world.
The "Qualcomm Timer" (QTMR) implements the ARM generic timer
specification, so the standard defines (CNTACR_BASE etc)
can be used.
- Make parts of the "APCS" register region available to the
non-secure world, e.g. for CPU frequency control implemented
in Linux.
- Initialize a platform-specific register to route all SMMU context
bank interrupts to the non-secure interrupt pin, since all control
of the SMMUs is left up to the non-secure world for now.
Change-Id: Icf676437b8e329dead06658e177107dfd0ba4f9d
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
60 lines
1.9 KiB
C
60 lines
1.9 KiB
C
/*
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* Copyright (c) 2021, Stephan Gerhold <stephan@gerhold.net>
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <common/debug.h>
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#include <drivers/arm/gicv2.h>
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#include <lib/mmio.h>
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#include "msm8916_gicv2.h"
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#include <msm8916_mmap.h>
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#define IRQ_SEC_SGI_0 8
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#define IRQ_SEC_SGI_1 9
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#define IRQ_SEC_SGI_2 10
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#define IRQ_SEC_SGI_3 11
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#define IRQ_SEC_SGI_4 12
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#define IRQ_SEC_SGI_5 13
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#define IRQ_SEC_SGI_6 14
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#define IRQ_SEC_SGI_7 15
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#define IRQ_SEC_PHY_TIMER (16 + 2) /* PPI #2 */
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static const interrupt_prop_t msm8916_interrupt_props[] = {
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INTR_PROP_DESC(IRQ_SEC_SGI_0, GIC_HIGHEST_SEC_PRIORITY,
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GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
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INTR_PROP_DESC(IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY,
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GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
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INTR_PROP_DESC(IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY,
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GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
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INTR_PROP_DESC(IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY,
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GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
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INTR_PROP_DESC(IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY,
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GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
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INTR_PROP_DESC(IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY,
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GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
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INTR_PROP_DESC(IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY,
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GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
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INTR_PROP_DESC(IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY,
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GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
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INTR_PROP_DESC(IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY,
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GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
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};
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static const gicv2_driver_data_t msm8916_gic_data = {
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.gicd_base = APCS_QGIC2_GICD,
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.gicc_base = APCS_QGIC2_GICC,
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.interrupt_props = msm8916_interrupt_props,
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.interrupt_props_num = ARRAY_SIZE(msm8916_interrupt_props),
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};
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void msm8916_gicv2_init(void)
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{
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gicv2_driver_init(&msm8916_gic_data);
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gicv2_distif_init();
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gicv2_pcpu_distif_init();
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gicv2_cpuif_enable();
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}
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