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af6447315c
Booting e.g. Linux in the non-secure world does not work with the
msm8916 port yet because essential hardware is not made available to
the non-secure world. Add more platform initialization to:
- Initialize the GICv2 and mark secure interrupts.
Only secure SGIs/PPIs so far. Override the GICD_PIDR2_GICV2
register address in platform_def.h to avoid a failing assert()
because of a (hardware) mistake in Qualcomm's GICv2 implementation.
- Make a timer frame available to the non-secure world.
The "Qualcomm Timer" (QTMR) implements the ARM generic timer
specification, so the standard defines (CNTACR_BASE etc)
can be used.
- Make parts of the "APCS" register region available to the
non-secure world, e.g. for CPU frequency control implemented
in Linux.
- Initialize a platform-specific register to route all SMMU context
bank interrupts to the non-secure interrupt pin, since all control
of the SMMUs is left up to the non-secure world for now.
Change-Id: Icf676437b8e329dead06658e177107dfd0ba4f9d
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
58 lines
1.8 KiB
C
58 lines
1.8 KiB
C
/*
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* Copyright (c) 2021, Stephan Gerhold <stephan@gerhold.net>
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef PLATFORM_DEF_H
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#define PLATFORM_DEF_H
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#include <plat/common/common_def.h>
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/*
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* There is at least 1 MiB available for BL31. However, at the moment the
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* "msm8916_entry_point" variable in the data section is read through the
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* 64 KiB region of the "boot remapper" after reset. For simplicity, limit
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* the end of the data section (BL31_PROGBITS_LIMIT) to 64 KiB for now and
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* the overall limit to 128 KiB. This could be increased if needed by placing
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* the "msm8916_entry_point" variable explicitly in the first 64 KiB of BL31.
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*/
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#define BL31_LIMIT (BL31_BASE + 0x20000) /* 128 KiB */
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#define BL31_PROGBITS_LIMIT (BL31_BASE + 0x10000) /* 64 KiB */
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#define CACHE_WRITEBACK_GRANULE U(64)
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#define PLATFORM_STACK_SIZE U(0x1000)
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/* CPU topology: single cluster with 4 cores */
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#define PLATFORM_CLUSTER_COUNT U(1)
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#define PLATFORM_MAX_CPUS_PER_CLUSTER U(4)
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#define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER_COUNT * \
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PLATFORM_MAX_CPUS_PER_CLUSTER)
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/* Power management */
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#define PLATFORM_SYSTEM_COUNT U(1)
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#define PLAT_NUM_PWR_DOMAINS (PLATFORM_SYSTEM_COUNT + \
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PLATFORM_CLUSTER_COUNT + \
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PLATFORM_CORE_COUNT)
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#define PLAT_MAX_PWR_LVL MPIDR_AFFLVL2
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#define PLAT_MAX_RET_STATE U(2)
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#define PLAT_MAX_OFF_STATE U(3)
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/* Translation tables */
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#define MAX_MMAP_REGIONS 8
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#define MAX_XLAT_TABLES 4
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#define PLAT_PHY_ADDR_SPACE_SIZE (ULL(1) << 32)
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#define PLAT_VIRT_ADDR_SPACE_SIZE (ULL(1) << 32)
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/* Timer frequency */
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#define PLAT_SYSCNT_FREQ 19200000
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/*
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* The Qualcomm QGIC2 implementation seems to have PIDR0-4 and PIDR4-7
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* erroneously swapped for some reason. PIDR2 is actually at 0xFD8.
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* Override the address in <drivers/arm/gicv2.h> to avoid a failing assert().
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*/
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#define GICD_PIDR2_GICV2 U(0xFD8)
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#endif /* PLATFORM_DEF_H */
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