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af6447315c
Booting e.g. Linux in the non-secure world does not work with the
msm8916 port yet because essential hardware is not made available to
the non-secure world. Add more platform initialization to:
- Initialize the GICv2 and mark secure interrupts.
Only secure SGIs/PPIs so far. Override the GICD_PIDR2_GICV2
register address in platform_def.h to avoid a failing assert()
because of a (hardware) mistake in Qualcomm's GICv2 implementation.
- Make a timer frame available to the non-secure world.
The "Qualcomm Timer" (QTMR) implements the ARM generic timer
specification, so the standard defines (CNTACR_BASE etc)
can be used.
- Make parts of the "APCS" register region available to the
non-secure world, e.g. for CPU frequency control implemented
in Linux.
- Initialize a platform-specific register to route all SMMU context
bank interrupts to the non-secure interrupt pin, since all control
of the SMMUs is left up to the non-secure world for now.
Change-Id: Icf676437b8e329dead06658e177107dfd0ba4f9d
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
42 lines
1.3 KiB
C
42 lines
1.3 KiB
C
/*
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* Copyright (c) 2021, Stephan Gerhold <stephan@gerhold.net>
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef MSM8916_MMAP_H
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#define MSM8916_MMAP_H
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#define PCNOC_BASE 0x00000000
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#define PCNOC_SIZE 0x8000000 /* 128 MiB */
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#define APCS_BASE 0x0b000000
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#define APCS_SIZE 0x800000 /* 8 MiB */
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#define MPM_BASE (PCNOC_BASE + 0x04a0000)
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#define MPM_PS_HOLD (MPM_BASE + 0xb000)
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#define TLMM_BASE (PCNOC_BASE + 0x1000000)
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#define TLMM_GPIO_CFG(n) (TLMM_BASE + ((n) * 0x1000))
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#define GCC_BASE (PCNOC_BASE + 0x1800000)
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#define APPS_SMMU_BASE (PCNOC_BASE + 0x1e00000)
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#define APPS_SMMU_QCOM (APPS_SMMU_BASE + 0xf0000)
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#define BLSP_UART1_BASE (PCNOC_BASE + 0x78af000)
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#define BLSP_UART2_BASE (PCNOC_BASE + 0x78b0000)
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#define APCS_QGIC2_BASE (APCS_BASE + 0x00000)
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#define APCS_QGIC2_GICD (APCS_QGIC2_BASE + 0x0000)
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#define APCS_QGIC2_GICC (APCS_QGIC2_BASE + 0x2000)
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#define APCS_BANKED_ACS (APCS_BASE + 0x08000)
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#define APCS_BANKED_SAW2 (APCS_BASE + 0x09000)
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#define APCS_CFG (APCS_BASE + 0x10000)
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#define APCS_GLB (APCS_BASE + 0x11000)
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#define APCS_L2_SAW2 (APCS_BASE + 0x12000)
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#define APCS_QTMR (APCS_BASE + 0x20000)
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#define APCS_ALIAS_ACS(cpu) (APCS_BASE + 0x88000 + ((cpu) * 0x10000))
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#define APCS_ALIAS_SAW2(cpu) (APCS_BASE + 0x89000 + ((cpu) * 0x10000))
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#endif /* MSM8916_MMAP_H */
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