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https://github.com/ARM-software/arm-trusted-firmware.git
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9df5ba05b4
LS1088A is a cost-effective, powerefficient, and highly integrated SoC device featuring eight extremely power-efficient 64-bit ARM Cortex-A53 cores with ECC-protected L1 and L2 cache memories for high reliability, running up to 1.6 GHz. This patch is to add ls1088a SoC support in TF-A. Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com> Signed-off-by: rocket <rod.dorris@nxp.com> Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com> Signed-off-by: Biwen Li <biwen.li@nxp.com> Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com> Change-Id: Id9ebcdad1beab07ea81a41955edd4f471d6cf090
88 lines
1.9 KiB
Modula-2
88 lines
1.9 KiB
Modula-2
#
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# Copyright 2022 NXP
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#
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# SPDX-License-Identifier: BSD-3-Clause
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#
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#
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#------------------------------------------------------------------------------
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#
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# This file contains the basic architecture definitions that drive the build
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#
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# -----------------------------------------------------------------------------
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CORE_TYPE := a53
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CACHE_LINE := 6
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# Set to GIC400 or GIC500
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GIC := GIC500
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# Set to CCI400 or CCN504 or CCN508
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INTERCONNECT := CCI400
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# Select the DDR PHY generation to be used
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PLAT_DDR_PHY := PHY_GEN1
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PHYS_SYS := 64
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# Indicate layerscape chassis level - set to 3=LSCH3 or 2=LSCH2
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CHASSIS := 3
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# TZC IP Details TZC used is TZC380 or TZC400
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TZC_ID := TZC400
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# CONSOLE Details available is NS16550 or PL011
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CONSOLE := NS16550
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NXP_SFP_VER := 3_4
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# In IMAGE_BL2, compile time flag for handling Cache coherency
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# with CAAM for BL2 running from OCRAM
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SEC_MEM_NON_COHERENT := yes
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# OCRAM MAP for BL2
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# Before BL2
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# 0x18000000 - 0x18009fff -> Used by ROM code, (TBD - can it be used for xlat tables)
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# 0x1800a000 - 0x1801Cfff -> Reserved for BL2 binary (76 KB)
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# 0x1801D000 - 0x1801ffff -> CSF header for BL2 (12 KB)
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OCRAM_START_ADDR := 0x18000000
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OCRAM_SIZE := 0x20000
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CSF_HDR_SZ := 0x3000
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# Area of OCRAM reserved by ROM code
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NXP_ROM_RSVD := 0xa000
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# Input to CST create_hdr_isbc tool
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BL2_HDR_LOC := 0x1801D000
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# Location of BL2 on OCRAM
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# BL2_BASE=OCRAM_START_ADDR+NXP_ROM_RSVD
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BL2_BASE := 0x1800a000
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# SoC ERRATUM to be enabled
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ERRATA_SOC_A008850 := 1
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# ARM Erratum
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ERRATA_A53_855873 := 1
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# DDR Erratum
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ERRATA_DDR_A008511 := 1
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ERRATA_DDR_A009803 := 1
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ERRATA_DDR_A009942 := 1
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ERRATA_DDR_A010165 := 1
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# Define Endianness of each module
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NXP_ESDHC_ENDIANNESS := LE
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NXP_SFP_ENDIANNESS := LE
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NXP_GPIO_ENDIANNESS := LE
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NXP_SNVS_ENDIANNESS := LE
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NXP_GUR_ENDIANNESS := LE
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NXP_SEC_ENDIANNESS := LE
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NXP_DDR_ENDIANNESS := LE
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NXP_QSPI_ENDIANNESS := LE
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# OCRAM ECC Enabled
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OCRAM_ECC_EN := yes
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