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https://github.com/ARM-software/arm-trusted-firmware.git
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c2d621db58
SMC call handling at EL3 due SIP and SVC calls. Signed-off-by: rocket <rod.dorris@nxp.com> Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com> Change-Id: If86ee43477fc3b6116623928a3299d4e9015df8c
153 lines
3.2 KiB
ArmAsm
153 lines
3.2 KiB
ArmAsm
/*
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* Copyright 2018-2020 NXP
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*
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*/
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#include <asm_macros.S>
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#include <bl31_data.h>
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.global el2_2_aarch32
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.global prefetch_disable
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#define SPSR_EL3_M4 0x10
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#define SPSR_EL_MASK 0xC
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#define SPSR_EL2 0x8
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#define SCR_EL3_4_EL2_AARCH32 0x131
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#define SPSR32_EL2_LE 0x1DA
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#define MIDR_PARTNUM_START 4
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#define MIDR_PARTNUM_WIDTH 12
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#define MIDR_PARTNUM_A53 0xD03
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#define MIDR_PARTNUM_A57 0xD07
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#define MIDR_PARTNUM_A72 0xD08
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/*
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* uint64_t el2_2_aarch32(u_register_t smc_id,
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* u_register_t start_addr,
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* u_register_t parm1,
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* u_register_t parm2)
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* this function allows changing the execution width of EL2 from Aarch64
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* to Aarch32
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* Note: MUST be called from EL2 @ Aarch64
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* in: x0 = smc function id
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* x1 = start address for EL2 @ Aarch32
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* x2 = first parameter to pass to EL2 @ Aarch32
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* x3 = second parameter to pass to EL2 @ Aarch32
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* out: x0 = 0, on success
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* x0 = -1, on failure
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* uses x0, x1, x2, x3
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*/
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func el2_2_aarch32
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/* check that caller is EL2 @ Aarch64 - err return if not */
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mrs x0, spsr_el3
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/* see if we were called from Aarch32 */
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tst x0, #SPSR_EL3_M4
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b.ne 2f
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/* see if we were called from EL2 */
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and x0, x0, SPSR_EL_MASK
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cmp x0, SPSR_EL2
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b.ne 2f
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/* set ELR_EL3 */
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msr elr_el3, x1
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/* set scr_el3 */
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mov x0, #SCR_EL3_4_EL2_AARCH32
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msr scr_el3, x0
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/* set sctlr_el2 */
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ldr x1, =SCTLR_EL2_RES1
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msr sctlr_el2, x1
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/* set spsr_el3 */
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ldr x0, =SPSR32_EL2_LE
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msr spsr_el3, x0
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/* x2 = parm 1
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* x3 = parm2
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*/
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/* set the parameters to be passed-thru to EL2 @ Aarch32 */
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mov x1, x2
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mov x2, x3
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/* x1 = parm 1
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* x2 = parm2
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*/
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mov x0, xzr
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/* invalidate the icache */
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ic iallu
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dsb sy
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isb
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b 1f
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2:
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/* error return */
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mvn x0, xzr
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ret
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1:
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eret
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endfunc el2_2_aarch32
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/*
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* int prefetch_disable(u_register_t smc_id, u_register_t mask)
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* this function marks cores which need to have the prefetch disabled -
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* secondary cores have prefetch disabled when they are released from reset -
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* the bootcore has prefetch disabled when this call is made
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* in: x0 = function id
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* x1 = core mask, where bit[0]=core0, bit[1]=core1, etc
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* if a bit in the mask is set, then prefetch is disabled for that
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* core
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* out: x0 = SMC_SUCCESS
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*/
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func prefetch_disable
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stp x4, x30, [sp, #-16]!
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mov x3, x1
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/* x1 = core prefetch disable mask */
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/* x3 = core prefetch disable mask */
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/* store the mask */
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mov x0, #PREFETCH_DIS_OFFSET
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bl _set_global_data
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/* x3 = core prefetch disable mask */
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/* see if we need to disable prefetch on THIS core */
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bl plat_my_core_mask
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/* x0 = core mask lsb */
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/* x3 = core prefetch disable mask */
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tst x3, x0
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b.eq 1f
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/* read midr_el1 */
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mrs x1, midr_el1
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/* x1 = midr_el1 */
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mov x0, xzr
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bfxil x0, x1, #MIDR_PARTNUM_START, #MIDR_PARTNUM_WIDTH
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/* x0 = part number (a53, a57, a72, etc) */
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/* branch on cpu-specific */
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cmp x0, #MIDR_PARTNUM_A57
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b.eq 1f
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cmp x0, #MIDR_PARTNUM_A72
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b.ne 1f
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bl _disable_ldstr_pfetch_A72
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b 1f
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1:
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ldp x4, x30, [sp], #16
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mov x0, xzr
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ret
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endfunc prefetch_disable
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