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https://github.com/ARM-software/arm-trusted-firmware.git
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1740ed1275
This patch adds memory barriers to the trampoline code copying TZDRAM contents to SysRAM during exit from System Suspend. These barriers make sure that all the copies go through before we start executing in SysRAM. Reported by: Nathan Tuck <ntuck@nvidia.com> Change-Id: I3fd2964086b6c0e044cc4165051a4801440db9cd Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
151 lines
3.5 KiB
ArmAsm
151 lines
3.5 KiB
ArmAsm
/*
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* Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <plat/common/common_def.h>
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#include <memctrl_v2.h>
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#include <tegra_def.h>
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#define TEGRA194_STATE_SYSTEM_SUSPEND 0x5C7
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#define TEGRA194_STATE_SYSTEM_RESUME 0x600D
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#define TEGRA194_MC_CTX_SIZE 0xFB
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.align 4
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.globl tegra194_cpu_reset_handler
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/* CPU reset handler routine */
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func tegra194_cpu_reset_handler
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/* check if we are exiting system suspend state */
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adr x0, __tegra194_system_suspend_state
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ldr x1, [x0]
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mov x2, #TEGRA194_STATE_SYSTEM_SUSPEND
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lsl x2, x2, #16
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add x2, x2, #TEGRA194_STATE_SYSTEM_SUSPEND
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cmp x1, x2
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bne boot_cpu
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/* set system resume state */
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mov x1, #TEGRA194_STATE_SYSTEM_RESUME
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lsl x1, x1, #16
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mov x2, #TEGRA194_STATE_SYSTEM_RESUME
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add x1, x1, x2
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str x1, [x0]
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dsb sy
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/* prepare to relocate to TZSRAM */
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mov x0, #BL31_BASE
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adr x1, __tegra194_cpu_reset_handler_end
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adr x2, __tegra194_cpu_reset_handler_data
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ldr x2, [x2, #8]
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/* memcpy16 */
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m_loop16:
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cmp x2, #16
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b.lt m_loop1
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ldp x3, x4, [x1], #16
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stp x3, x4, [x0], #16
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sub x2, x2, #16
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b m_loop16
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/* copy byte per byte */
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m_loop1:
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cbz x2, boot_cpu
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ldrb w3, [x1], #1
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strb w3, [x0], #1
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subs x2, x2, #1
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b.ne m_loop1
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/*
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* Synchronization barriers to make sure that memory is flushed out
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* before we start execution in SysRAM.
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*/
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dsb sy
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isb
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boot_cpu:
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adr x0, __tegra194_cpu_reset_handler_data
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ldr x0, [x0]
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br x0
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endfunc tegra194_cpu_reset_handler
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/*
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* Tegra194 reset data (offset 0x0 - 0x2490)
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*
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* 0x0000: secure world's entrypoint
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* 0x0008: BL31 size (RO + RW)
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* 0x0010: MC context start
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* 0x2490: MC context end
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*/
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.align 4
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.type __tegra194_cpu_reset_handler_data, %object
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.globl __tegra194_cpu_reset_handler_data
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__tegra194_cpu_reset_handler_data:
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.quad tegra_secure_entrypoint
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.quad __BL31_END__ - BL31_BASE
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.globl __tegra194_system_suspend_state
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__tegra194_system_suspend_state:
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.quad 0
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.align 4
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__tegra194_mc_context:
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.rept TEGRA194_MC_CTX_SIZE
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.quad 0
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.endr
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.size __tegra194_cpu_reset_handler_data, \
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. - __tegra194_cpu_reset_handler_data
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.align 4
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.globl __tegra194_cpu_reset_handler_end
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__tegra194_cpu_reset_handler_end:
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.globl tegra194_get_cpu_reset_handler_size
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.globl tegra194_get_cpu_reset_handler_base
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.globl tegra194_get_mc_ctx_offset
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.globl tegra194_set_system_suspend_entry
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/* return size of the CPU reset handler */
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func tegra194_get_cpu_reset_handler_size
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adr x0, __tegra194_cpu_reset_handler_end
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adr x1, tegra194_cpu_reset_handler
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sub x0, x0, x1
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ret
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endfunc tegra194_get_cpu_reset_handler_size
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/* return the start address of the CPU reset handler */
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func tegra194_get_cpu_reset_handler_base
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adr x0, tegra194_cpu_reset_handler
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ret
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endfunc tegra194_get_cpu_reset_handler_base
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/* return the size of the MC context */
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func tegra194_get_mc_ctx_offset
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adr x0, __tegra194_mc_context
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adr x1, tegra194_cpu_reset_handler
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sub x0, x0, x1
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ret
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endfunc tegra194_get_mc_ctx_offset
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/* set system suspend state before SC7 entry */
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func tegra194_set_system_suspend_entry
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mov x0, #TEGRA_MC_BASE
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mov x3, #MC_SECURITY_CFG3_0
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ldr w1, [x0, x3]
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lsl x1, x1, #32
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mov x3, #MC_SECURITY_CFG0_0
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ldr w2, [x0, x3]
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orr x3, x1, x2 /* TZDRAM base */
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adr x0, __tegra194_system_suspend_state
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adr x1, tegra194_cpu_reset_handler
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sub x2, x0, x1 /* offset in TZDRAM */
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mov x0, #TEGRA194_STATE_SYSTEM_SUSPEND
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lsl x0, x0, #16
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add x0, x0, #TEGRA194_STATE_SYSTEM_SUSPEND
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str x0, [x3, x2] /* set value in TZDRAM */
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dsb sy
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ret
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endfunc tegra194_set_system_suspend_entry
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