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https://github.com/ARM-software/arm-trusted-firmware.git
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2561cb50f1
MMIO writes should verify that the writes actually went through. Read the value back after the write operation, perform assert if the read back value is not same as the write value. Change-Id: Id2ceb014116f3aa6a9e86505ca1ae9911470a679 Signed-off-by: Anthony Zhou <anzhou@nvidia.com>
76 lines
2.8 KiB
C
76 lines
2.8 KiB
C
/*
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* Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <string.h>
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#include <arch_helpers.h>
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#include <common/debug.h>
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#include <lib/mmio.h>
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#include <mce.h>
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#include <tegra194_private.h>
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#include <tegra_def.h>
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#include <tegra_private.h>
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extern uint64_t tegra_bl31_phys_base;
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#define MISCREG_AA64_RST_LOW 0x2004U
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#define MISCREG_AA64_RST_HIGH 0x2008U
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#define CPU_RESET_MODE_AA64 1U
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/*******************************************************************************
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* Setup secondary CPU vectors
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******************************************************************************/
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void plat_secondary_setup(void)
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{
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uint32_t addr_low, addr_high;
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plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params();
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uint64_t cpu_reset_handler_base, cpu_reset_handler_size, tzdram_addr;
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uint64_t src_len_bytes = BL_END - tegra_bl31_phys_base;
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INFO("Setting up secondary CPU boot\n");
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tzdram_addr = params_from_bl2->tzdram_base +
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tegra194_get_cpu_reset_handler_size();
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/*
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* The BL31 code resides in the TZSRAM which loses state
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* when we enter System Suspend. Copy the wakeup trampoline
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* code to TZDRAM to help us exit from System Suspend.
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*/
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cpu_reset_handler_base = tegra194_get_cpu_reset_handler_base();
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cpu_reset_handler_size = tegra194_get_cpu_reset_handler_size();
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memcpy((void *)((uintptr_t)params_from_bl2->tzdram_base),
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(void *)((uintptr_t)cpu_reset_handler_base),
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cpu_reset_handler_size);
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/* TZDRAM base will be used as the "resume" address */
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addr_low = (uint32_t)params_from_bl2->tzdram_base | CPU_RESET_MODE_AA64;
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addr_high = (uint32_t)((params_from_bl2->tzdram_base >> 32U) & 0x7ffU);
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/* write lower 32 bits first, then the upper 11 bits */
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mmio_write_32(TEGRA_MISC_BASE + MISCREG_AA64_RST_LOW, addr_low);
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assert(mmio_read_32(TEGRA_MISC_BASE + MISCREG_AA64_RST_LOW) == addr_low);
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mmio_write_32(TEGRA_MISC_BASE + MISCREG_AA64_RST_HIGH, addr_high);
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assert(mmio_read_32(TEGRA_MISC_BASE + MISCREG_AA64_RST_HIGH) == addr_high);
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/* save reset vector to be used during SYSTEM_SUSPEND exit */
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mmio_write_32(TEGRA_SCRATCH_BASE + SCRATCH_RESET_VECTOR_LO,
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addr_low);
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assert(mmio_read_32(TEGRA_SCRATCH_BASE + SCRATCH_RESET_VECTOR_LO) == addr_low);
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mmio_write_32(TEGRA_SCRATCH_BASE + SCRATCH_RESET_VECTOR_HI,
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addr_high);
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assert(mmio_read_32(TEGRA_SCRATCH_BASE + SCRATCH_RESET_VECTOR_HI) == addr_high);
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mmio_write_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV72_LO,
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(uint32_t)tzdram_addr);
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assert(mmio_read_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV72_LO) == (uint32_t)tzdram_addr);
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mmio_write_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV72_HI,
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(uint32_t)src_len_bytes);
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assert(mmio_read_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV72_HI) == (uint32_t)src_len_bytes);
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}
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