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https://github.com/ARM-software/arm-trusted-firmware.git
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2139c9c8bf
TZSRAM loses power during System suspend, so the entire contents are copied to TZDRAM before Sysem Suspend entry. The warmboot code verifies and restores the contents to TZSRAM during System Resume. This patch removes the code that sets up CPU vector to point to TZSRAM during System Resume as a result. The trampoline code can also be completely removed as a result. Change-Id: I2830eb1db16efef3dfd96c4e3afc41a307588ca1 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
42 lines
1.2 KiB
C
42 lines
1.2 KiB
C
/*
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* Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <string.h>
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#include <arch_helpers.h>
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#include <common/debug.h>
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#include <lib/mmio.h>
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#include <mce.h>
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#include <tegra_def.h>
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#include <tegra_private.h>
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#define SCRATCH_SECURE_RSV1_SCRATCH_0 0x658U
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#define SCRATCH_SECURE_RSV1_SCRATCH_1 0x65CU
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#define CPU_RESET_MODE_AA64 1U
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/*******************************************************************************
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* Setup secondary CPU vectors
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******************************************************************************/
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void plat_secondary_setup(void)
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{
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uint32_t addr_low, addr_high;
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INFO("Setting up secondary CPU boot\n");
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/* TZDRAM base will be used as the "resume" address */
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addr_low = (uintptr_t)&tegra_secure_entrypoint | CPU_RESET_MODE_AA64;
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addr_high = (uintptr_t)(((uintptr_t)&tegra_secure_entrypoint >> 32U) & 0x7ffU);
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/* save reset vector to be used during SYSTEM_SUSPEND exit */
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mmio_write_32(TEGRA_SCRATCH_BASE + SCRATCH_RESET_VECTOR_LO,
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addr_low);
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mmio_write_32(TEGRA_SCRATCH_BASE + SCRATCH_RESET_VECTOR_HI,
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addr_high);
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}
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