mirror of
https://github.com/ARM-software/arm-trusted-firmware.git
synced 2025-08-16 09:27:01 +02:00
09d40e0e08
Enforce full include path for includes. Deprecate old paths.
The following folders inside include/lib have been left unchanged:
- include/lib/cpus/${ARCH}
- include/lib/el3_runtime/${ARCH}
The reason for this change is that having a global namespace for
includes isn't a good idea. It defeats one of the advantages of having
folders and it introduces problems that are sometimes subtle (because
you may not know the header you are actually including if there are two
of them).
For example, this patch had to be created because two headers were
called the same way: e0ea0928d5 ("Fix gpio includes of mt8173 platform
to avoid collision."). More recently, this patch has had similar
problems: 46f9b2c3a2 ("drivers: add tzc380 support").
This problem was introduced in commit 4ecca33988 ("Move include and
source files to logical locations"). At that time, there weren't too
many headers so it wasn't a real issue. However, time has shown that
this creates problems.
Platforms that want to preserve the way they include headers may add the
removed paths to PLAT_INCLUDES, but this is discouraged.
Change-Id: I39dc53ed98f9e297a5966e723d1936d6ccf2fc8f
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
58 lines
1.7 KiB
C
58 lines
1.7 KiB
C
/*
|
|
* Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
|
|
*
|
|
* SPDX-License-Identifier: BSD-3-Clause
|
|
*/
|
|
|
|
#ifndef MEMCTRL_V1_H
|
|
#define MEMCTRL_V1_H
|
|
|
|
#include <lib/mmio.h>
|
|
|
|
#include <tegra_def.h>
|
|
|
|
/* SMMU registers */
|
|
#define MC_SMMU_CONFIG_0 0x10U
|
|
#define MC_SMMU_CONFIG_0_SMMU_ENABLE_DISABLE 0U
|
|
#define MC_SMMU_CONFIG_0_SMMU_ENABLE_ENABLE 1U
|
|
#define MC_SMMU_TLB_CONFIG_0 0x14U
|
|
#define MC_SMMU_TLB_CONFIG_0_RESET_VAL 0x20000010U
|
|
#define MC_SMMU_PTC_CONFIG_0 0x18U
|
|
#define MC_SMMU_PTC_CONFIG_0_RESET_VAL 0x2000003fU
|
|
#define MC_SMMU_TLB_FLUSH_0 0x30U
|
|
#define TLB_FLUSH_VA_MATCH_ALL 0U
|
|
#define TLB_FLUSH_ASID_MATCH_DISABLE 0U
|
|
#define TLB_FLUSH_ASID_MATCH_SHIFT 31U
|
|
#define MC_SMMU_TLB_FLUSH_ALL \
|
|
(TLB_FLUSH_VA_MATCH_ALL | \
|
|
(TLB_FLUSH_ASID_MATCH_DISABLE << TLB_FLUSH_ASID_MATCH_SHIFT))
|
|
#define MC_SMMU_PTC_FLUSH_0 0x34U
|
|
#define MC_SMMU_PTC_FLUSH_ALL 0U
|
|
#define MC_SMMU_ASID_SECURITY_0 0x38U
|
|
#define MC_SMMU_ASID_SECURITY 0U
|
|
#define MC_SMMU_TRANSLATION_ENABLE_0_0 0x228U
|
|
#define MC_SMMU_TRANSLATION_ENABLE_1_0 0x22cU
|
|
#define MC_SMMU_TRANSLATION_ENABLE_2_0 0x230U
|
|
#define MC_SMMU_TRANSLATION_ENABLE_3_0 0x234U
|
|
#define MC_SMMU_TRANSLATION_ENABLE_4_0 0xb98U
|
|
#define MC_SMMU_TRANSLATION_ENABLE (~0)
|
|
|
|
/* MC IRAM aperture registers */
|
|
#define MC_IRAM_BASE_LO 0x65CU
|
|
#define MC_IRAM_TOP_LO 0x660U
|
|
#define MC_IRAM_BASE_TOP_HI 0x980U
|
|
#define MC_IRAM_REG_CTRL 0x964U
|
|
#define MC_DISABLE_IRAM_CFG_WRITES 1U
|
|
|
|
static inline uint32_t tegra_mc_read_32(uint32_t off)
|
|
{
|
|
return mmio_read_32(TEGRA_MC_BASE + off);
|
|
}
|
|
|
|
static inline void tegra_mc_write_32(uint32_t off, uint32_t val)
|
|
{
|
|
mmio_write_32(TEGRA_MC_BASE + off, val);
|
|
}
|
|
|
|
#endif /* MEMCTRL_V1_H */
|