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https://github.com/ARM-software/arm-trusted-firmware.git
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21ec61a904
The SMMU configuration can get corrupted or updated by external clients during boot without our knowledge. This patch introduces a "verify" function for the SMMU driver, to check that the boot configuration settings are intact. Usually, this function should be called at the end of the boot cycle. This function only calls panic() on silicon platforms. Change-Id: I2ab45a7f228781e71c73ba1f4ffc49353effe146 Signed-off-by: George Bauernschmidt <georgeb@nvidia.com>
122 lines
3.8 KiB
C
122 lines
3.8 KiB
C
/*
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* Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <string.h>
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#include <platform_def.h>
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#include <common/bl_common.h>
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#include <common/debug.h>
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#include <smmu.h>
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#include <tegra_platform.h>
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#include <tegra_private.h>
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extern void memcpy16(void *dest, const void *src, unsigned int length);
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#define SMMU_NUM_CONTEXTS 64U
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#define SMMU_CONTEXT_BANK_MAX_IDX 64U
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#define MISMATCH_DETECTED 0x55AA55AAU
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/*
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* Init SMMU during boot or "System Suspend" exit
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*/
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void tegra_smmu_init(void)
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{
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uint32_t val, cb_idx, smmu_id, ctx_base;
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uint32_t num_smmu_devices = plat_get_num_smmu_devices();
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for (smmu_id = 0U; smmu_id < num_smmu_devices; smmu_id++) {
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/* Program the SMMU pagesize and reset CACHE_LOCK bit */
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val = tegra_smmu_read_32(smmu_id, SMMU_GSR0_SECURE_ACR);
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val |= SMMU_GSR0_PGSIZE_64K;
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val &= (uint32_t)~SMMU_ACR_CACHE_LOCK_ENABLE_BIT;
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tegra_smmu_write_32(smmu_id, SMMU_GSR0_SECURE_ACR, val);
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/* reset CACHE LOCK bit for NS Aux. Config. Register */
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val = tegra_smmu_read_32(smmu_id, SMMU_GNSR_ACR);
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val &= (uint32_t)~SMMU_ACR_CACHE_LOCK_ENABLE_BIT;
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tegra_smmu_write_32(smmu_id, SMMU_GNSR_ACR, val);
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/* disable TCU prefetch for all contexts */
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ctx_base = (SMMU_GSR0_PGSIZE_64K * SMMU_NUM_CONTEXTS)
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+ SMMU_CBn_ACTLR;
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for (cb_idx = 0U; cb_idx < SMMU_CONTEXT_BANK_MAX_IDX; cb_idx++) {
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val = tegra_smmu_read_32(smmu_id,
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ctx_base + (SMMU_GSR0_PGSIZE_64K * cb_idx));
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val &= (uint32_t)~SMMU_CBn_ACTLR_CPRE_BIT;
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tegra_smmu_write_32(smmu_id, ctx_base +
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(SMMU_GSR0_PGSIZE_64K * cb_idx), val);
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}
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/* set CACHE LOCK bit for NS Aux. Config. Register */
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val = tegra_smmu_read_32(smmu_id, SMMU_GNSR_ACR);
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val |= (uint32_t)SMMU_ACR_CACHE_LOCK_ENABLE_BIT;
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tegra_smmu_write_32(smmu_id, SMMU_GNSR_ACR, val);
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/* set CACHE LOCK bit for S Aux. Config. Register */
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val = tegra_smmu_read_32(smmu_id, SMMU_GSR0_SECURE_ACR);
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val |= (uint32_t)SMMU_ACR_CACHE_LOCK_ENABLE_BIT;
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tegra_smmu_write_32(smmu_id, SMMU_GSR0_SECURE_ACR, val);
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}
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}
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/*
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* Verify SMMU settings have not been altered during boot
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*/
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void tegra_smmu_verify(void)
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{
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uint32_t cb_idx, ctx_base, smmu_id, val;
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uint32_t num_smmu_devices = plat_get_num_smmu_devices();
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uint32_t mismatch = 0U;
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for (smmu_id = 0U; smmu_id < num_smmu_devices; smmu_id++) {
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/* check PGSIZE_64K bit inr S Aux. Config. Register */
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val = tegra_smmu_read_32(smmu_id, SMMU_GSR0_SECURE_ACR);
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if (0U == (val & SMMU_GSR0_PGSIZE_64K)) {
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ERROR("%s: PGSIZE_64K Mismatch - smmu_id=%d, GSR0_SECURE_ACR=%x\n",
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__func__, smmu_id, val);
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mismatch = MISMATCH_DETECTED;
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}
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/* check CACHE LOCK bit in S Aux. Config. Register */
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if (0U == (val & SMMU_ACR_CACHE_LOCK_ENABLE_BIT)) {
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ERROR("%s: CACHE_LOCK Mismatch - smmu_id=%d, GSR0_SECURE_ACR=%x\n",
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__func__, smmu_id, val);
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mismatch = MISMATCH_DETECTED;
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}
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/* check CACHE LOCK bit in NS Aux. Config. Register */
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val = tegra_smmu_read_32(smmu_id, SMMU_GNSR_ACR);
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if (0U == (val & SMMU_ACR_CACHE_LOCK_ENABLE_BIT)) {
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ERROR("%s: Mismatch - smmu_id=%d, GNSR_ACR=%x\n",
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__func__, smmu_id, val);
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mismatch = MISMATCH_DETECTED;
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}
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/* verify TCU prefetch for all contexts is disabled */
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ctx_base = (SMMU_GSR0_PGSIZE_64K * SMMU_NUM_CONTEXTS) +
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SMMU_CBn_ACTLR;
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for (cb_idx = 0U; cb_idx < SMMU_CONTEXT_BANK_MAX_IDX; cb_idx++) {
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val = tegra_smmu_read_32(smmu_id,
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ctx_base + (SMMU_GSR0_PGSIZE_64K * cb_idx));
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if (0U != (val & SMMU_CBn_ACTLR_CPRE_BIT)) {
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ERROR("%s: Mismatch - smmu_id=%d, cb_idx=%d, GSR0_PGSIZE_64K=%x\n",
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__func__, smmu_id, cb_idx, val);
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mismatch = MISMATCH_DETECTED;
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}
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}
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}
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/* Treat configuration mismatch as fatal */
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if ((mismatch == MISMATCH_DETECTED) && tegra_platform_is_silicon()) {
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panic();
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}
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}
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