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https://github.com/ARM-software/arm-trusted-firmware.git
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e2469d823b
This patch moves the 'drivers' and the 'lib' folders out of the 'common' folder. This way the 'common' folder shall contain only the platform support required for all Tegra platforms. Change-Id: I2f238572d0a078d60c6b458a559538dc8a4d1856 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
128 lines
3.1 KiB
C
128 lines
3.1 KiB
C
/*
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* Copyright (c) 2017-2020, NVIDIA CORPORATION. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef BPMP_INTF_H
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#define BPMP_INTF_H
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/**
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* Flags used in IPC req
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*/
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#define FLAG_DO_ACK (U(1) << 0)
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#define FLAG_RING_DOORBELL (U(1) << 1)
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/* Bit 1 is designated for CCPlex in secure world */
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#define HSP_MASTER_CCPLEX_BIT (U(1) << 1)
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/* Bit 19 is designated for BPMP in non-secure world */
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#define HSP_MASTER_BPMP_BIT (U(1) << 19)
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/* Timeout to receive response from BPMP is 1 sec */
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#define TIMEOUT_RESPONSE_FROM_BPMP_US U(1000000) /* in microseconds */
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/**
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* IVC protocol defines and command/response frame
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*/
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/**
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* IVC specific defines
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*/
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#define IVC_CMD_SZ_BYTES U(128)
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#define IVC_DATA_SZ_BYTES U(120)
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/**
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* Holds frame data for an IPC request
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*/
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struct frame_data {
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/* Identification as to what kind of data is being transmitted */
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uint32_t mrq;
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/* Flags for slave as to how to respond back */
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uint32_t flags;
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/* Actual data being sent */
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uint8_t data[IVC_DATA_SZ_BYTES];
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};
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/**
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* Commands send to the BPMP firmware
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*/
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/**
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* MRQ command codes
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*/
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#define MRQ_RESET U(20)
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#define MRQ_CLK U(22)
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/**
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* Reset sub-commands
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*/
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#define CMD_RESET_ASSERT U(1)
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#define CMD_RESET_DEASSERT U(2)
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#define CMD_RESET_MODULE U(3)
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/**
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* Used by the sender of an #MRQ_RESET message to request BPMP to
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* assert or deassert a given reset line.
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*/
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struct __attribute__((packed)) mrq_reset_request {
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/* reset action to perform (mrq_reset_commands) */
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uint32_t cmd;
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/* id of the reset to affected */
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uint32_t reset_id;
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};
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/**
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* MRQ_CLK sub-commands
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*
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*/
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enum {
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CMD_CLK_GET_RATE = U(1),
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CMD_CLK_SET_RATE = U(2),
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CMD_CLK_ROUND_RATE = U(3),
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CMD_CLK_GET_PARENT = U(4),
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CMD_CLK_SET_PARENT = U(5),
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CMD_CLK_IS_ENABLED = U(6),
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CMD_CLK_ENABLE = U(7),
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CMD_CLK_DISABLE = U(8),
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CMD_CLK_GET_ALL_INFO = U(14),
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CMD_CLK_GET_MAX_CLK_ID = U(15),
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CMD_CLK_MAX,
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};
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/**
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* Used by the sender of an #MRQ_CLK message to control clocks. The
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* clk_request is split into several sub-commands. Some sub-commands
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* require no additional data. Others have a sub-command specific
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* payload
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*
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* |sub-command |payload |
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* |----------------------------|-----------------------|
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* |CMD_CLK_GET_RATE |- |
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* |CMD_CLK_SET_RATE |clk_set_rate |
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* |CMD_CLK_ROUND_RATE |clk_round_rate |
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* |CMD_CLK_GET_PARENT |- |
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* |CMD_CLK_SET_PARENT |clk_set_parent |
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* |CMD_CLK_IS_ENABLED |- |
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* |CMD_CLK_ENABLE |- |
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* |CMD_CLK_DISABLE |- |
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* |CMD_CLK_GET_ALL_INFO |- |
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* |CMD_CLK_GET_MAX_CLK_ID |- |
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*
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*/
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struct mrq_clk_request {
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/**
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* sub-command and clock id concatenated to 32-bit word.
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* - bits[31..24] is the sub-cmd.
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* - bits[23..0] is the clock id
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*/
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uint32_t cmd_and_id;
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};
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/**
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* Macro to prepare the MRQ_CLK sub-command
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*/
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#define make_mrq_clk_cmd(cmd, id) (((cmd) << 24) | (id & 0xFFFFFF))
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#endif /* BPMP_INTF_H */
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