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https://github.com/ARM-software/arm-trusted-firmware.git
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296b590206
The clock and pll of mt8195 can be locked into security access by device apc. Add clock and pll related SiP call for the access from Kernel space. Signed-off-by: Flora Fu <flora.fu@mediatek.com> Change-Id: I0c1f7d6c6abdd3b976492a0b776dc5b1d1f1512b
52 lines
1.5 KiB
C
52 lines
1.5 KiB
C
/*
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* Copyright (c) 2021, MediaTek Inc. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef MTK_APUSYS_H
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#define MTK_APUSYS_H
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#include <stdint.h>
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/* setup the SMC command ops */
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#define MTK_SIP_APU_START_MCU (0x00U)
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#define MTK_SIP_APU_STOP_MCU (0x01U)
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#define MTK_SIP_APUPWR_BUS_PROT_CG_ON (0x02U)
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#define MTK_SIP_APUPWR_BULK_PLL (0x03U)
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#define MTK_SIP_APUPWR_ACC_INIT_ALL (0x04U)
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#define MTK_SIP_APUPWR_ACC_TOP (0x05U)
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/* AO Register */
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#define AO_MD32_PRE_DEFINE (APUSYS_APU_S_S_4_BASE + 0x00)
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#define AO_MD32_BOOT_CTRL (APUSYS_APU_S_S_4_BASE + 0x04)
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#define AO_MD32_SYS_CTRL (APUSYS_APU_S_S_4_BASE + 0x08)
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#define AO_SEC_FW (APUSYS_APU_S_S_4_BASE + 0x10)
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#define AO_SEC_USR_FW (APUSYS_APU_S_S_4_BASE + 0x14)
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#define PRE_DEFINE_CACHE_TCM (0x3U)
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#define PRE_DEFINE_CACHE (0x2U)
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#define PRE_DEFINE_SHIFT_0G (0U)
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#define PRE_DEFINE_SHIFT_1G (2U)
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#define PRE_DEFINE_SHIFT_2G (4U)
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#define PRE_DEFINE_SHIFT_3G (6U)
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#define SEC_FW_NON_SECURE (1U)
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#define SEC_FW_SHIFT_NS (4U)
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#define SEC_FW_DOMAIN_SHIFT (0U)
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#define SEC_USR_FW_NON_SECURE (1U)
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#define SEC_USR_FW_SHIFT_NS (4U)
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#define SEC_USR_FW_DOMAIN_SHIFT (0U)
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#define SYS_CTRL_RUN (0U)
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#define SYS_CTRL_STALL (1U)
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/* Reviser Register */
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#define REVISER_SECUREFW_CTXT (APUSYS_SCTRL_REVISER_BASE + 0x100)
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#define REVISER_USDRFW_CTXT (APUSYS_SCTRL_REVISER_BASE + 0x104)
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int32_t apusys_kernel_ctrl(uint64_t x1, uint64_t x2, uint64_t x3, uint64_t x4,
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uint32_t *ret1);
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#endif /* MTK_APUSYS_H */
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