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https://github.com/ARM-software/arm-trusted-firmware.git
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296b590206
The clock and pll of mt8195 can be locked into security access by device apc. Add clock and pll related SiP call for the access from Kernel space. Signed-off-by: Flora Fu <flora.fu@mediatek.com> Change-Id: I0c1f7d6c6abdd3b976492a0b776dc5b1d1f1512b
84 lines
2.2 KiB
C
84 lines
2.2 KiB
C
/*
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* Copyright (c) 2021, MediaTek Inc. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <common/debug.h>
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#include <drivers/console.h>
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#include <lib/mmio.h>
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#include <apupwr_clkctl.h>
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#include <mtk_apusys.h>
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#include <plat/common/platform.h>
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int32_t apusys_kernel_ctrl(uint64_t x1, uint64_t x2, uint64_t x3, uint64_t x4,
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uint32_t *ret1)
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{
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int32_t ret = 0L;
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uint32_t request_ops;
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request_ops = (uint32_t)x1;
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switch (request_ops) {
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case MTK_SIP_APU_START_MCU:
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/* setup addr[33:32] in reviser */
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mmio_write_32(REVISER_SECUREFW_CTXT, 0U);
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mmio_write_32(REVISER_USDRFW_CTXT, 0U);
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/* setup secure sideband */
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mmio_write_32(AO_SEC_FW,
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(SEC_FW_NON_SECURE << SEC_FW_SHIFT_NS) |
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(0U << SEC_FW_DOMAIN_SHIFT));
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/* setup boot address */
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mmio_write_32(AO_MD32_BOOT_CTRL, 0U);
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/* setup pre-define region */
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mmio_write_32(AO_MD32_PRE_DEFINE,
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(PRE_DEFINE_CACHE_TCM << PRE_DEFINE_SHIFT_0G) |
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(PRE_DEFINE_CACHE << PRE_DEFINE_SHIFT_1G) |
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(PRE_DEFINE_CACHE << PRE_DEFINE_SHIFT_2G) |
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(PRE_DEFINE_CACHE << PRE_DEFINE_SHIFT_3G));
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/* release runstall */
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mmio_write_32(AO_MD32_SYS_CTRL, SYS_CTRL_RUN);
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INFO("[APUSYS] rev(0x%08x,0x%08x)\n",
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mmio_read_32(REVISER_SECUREFW_CTXT),
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mmio_read_32(REVISER_USDRFW_CTXT));
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INFO("[APUSYS] ao(0x%08x,0x%08x,0x%08x,0x%08x,0x%08x)\n",
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mmio_read_32(AO_SEC_FW),
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mmio_read_32(AO_SEC_USR_FW),
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mmio_read_32(AO_MD32_BOOT_CTRL),
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mmio_read_32(AO_MD32_PRE_DEFINE),
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mmio_read_32(AO_MD32_SYS_CTRL));
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break;
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case MTK_SIP_APU_STOP_MCU:
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/* hold runstall */
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mmio_write_32(AO_MD32_SYS_CTRL, SYS_CTRL_STALL);
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INFO("[APUSYS] md32_boot_ctrl=0x%08x,runstall=0x%08x\n",
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mmio_read_32(AO_MD32_BOOT_CTRL),
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mmio_read_32(AO_MD32_SYS_CTRL));
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break;
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case MTK_SIP_APUPWR_BUS_PROT_CG_ON:
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apupwr_smc_bus_prot_cg_on();
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break;
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case MTK_SIP_APUPWR_BULK_PLL:
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ret = apupwr_smc_bulk_pll((bool)x2);
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break;
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case MTK_SIP_APUPWR_ACC_INIT_ALL:
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ret = apupwr_smc_acc_init_all();
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break;
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case MTK_SIP_APUPWR_ACC_TOP:
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apupwr_smc_acc_top((bool)x2);
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break;
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default:
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ERROR("%s, unknown request_ops=0x%x\n", __func__, request_ops);
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break;
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}
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return ret;
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}
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