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09d40e0e08
Enforce full include path for includes. Deprecate old paths.
The following folders inside include/lib have been left unchanged:
- include/lib/cpus/${ARCH}
- include/lib/el3_runtime/${ARCH}
The reason for this change is that having a global namespace for
includes isn't a good idea. It defeats one of the advantages of having
folders and it introduces problems that are sometimes subtle (because
you may not know the header you are actually including if there are two
of them).
For example, this patch had to be created because two headers were
called the same way: e0ea0928d5 ("Fix gpio includes of mt8173 platform
to avoid collision."). More recently, this patch has had similar
problems: 46f9b2c3a2 ("drivers: add tzc380 support").
This problem was introduced in commit 4ecca33988 ("Move include and
source files to logical locations"). At that time, there weren't too
many headers so it wasn't a real issue. However, time has shown that
this creates problems.
Platforms that want to preserve the way they include headers may add the
removed paths to PLAT_INCLUDES, but this is discouraged.
Change-Id: I39dc53ed98f9e297a5966e723d1936d6ccf2fc8f
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
221 lines
5.5 KiB
C
221 lines
5.5 KiB
C
/*
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* Copyright (c) 2014-2017, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef MCUCFG_H
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#define MCUCFG_H
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#include <stdint.h>
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#include <mt8173_def.h>
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struct mt8173_mcucfg_regs {
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uint32_t mp0_ca7l_cache_config;
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struct {
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uint32_t mem_delsel0;
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uint32_t mem_delsel1;
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} mp0_cpu[4];
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uint32_t mp0_cache_mem_delsel0;
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uint32_t mp0_cache_mem_delsel1;
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uint32_t mp0_axi_config;
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uint32_t mp0_misc_config[2];
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struct {
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uint32_t rv_addr_lw;
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uint32_t rv_addr_hw;
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} mp0_rv_addr[4];
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uint32_t mp0_ca7l_cfg_dis;
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uint32_t mp0_ca7l_clken_ctrl;
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uint32_t mp0_ca7l_rst_ctrl;
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uint32_t mp0_ca7l_misc_config;
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uint32_t mp0_ca7l_dbg_pwr_ctrl;
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uint32_t mp0_rw_rsvd0;
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uint32_t mp0_rw_rsvd1;
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uint32_t mp0_ro_rsvd;
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uint32_t reserved0_0[100];
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uint32_t mp1_cpucfg;
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uint32_t mp1_miscdbg;
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uint32_t reserved0_1[13];
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uint32_t mp1_rst_ctl;
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uint32_t mp1_clkenm_div;
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uint32_t reserved0_2[7];
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uint32_t mp1_config_res;
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uint32_t reserved0_3[13];
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struct {
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uint32_t rv_addr_lw;
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uint32_t rv_addr_hw;
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} mp1_rv_addr[2];
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uint32_t reserved0_4[84];
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uint32_t mp0_rst_status; /* 0x400 */
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uint32_t mp0_dbg_ctrl;
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uint32_t mp0_dbg_flag;
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uint32_t mp0_ca7l_ir_mon;
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struct {
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uint32_t pc_lw;
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uint32_t pc_hw;
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uint32_t fp_arch32;
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uint32_t sp_arch32;
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uint32_t fp_arch64_lw;
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uint32_t fp_arch64_hw;
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uint32_t sp_arch64_lw;
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uint32_t sp_arch64_hw;
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} mp0_dbg_core[4];
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uint32_t dfd_ctrl;
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uint32_t dfd_cnt_l;
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uint32_t dfd_cnt_h;
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uint32_t misccfg_mp0_rw_rsvd;
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uint32_t misccfg_sec_vio_status0;
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uint32_t misccfg_sec_vio_status1;
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uint32_t reserved1[22];
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uint32_t misccfg_rw_rsvd; /* 0x500 */
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uint32_t mcusys_dbg_mon_sel_a;
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uint32_t mcusys_dbg_mon;
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uint32_t reserved2[61];
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uint32_t mcusys_config_a; /* 0x600 */
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uint32_t mcusys_config1_a;
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uint32_t mcusys_gic_peribase_a;
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uint32_t reserved3;
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uint32_t sec_range0_start; /* 0x610 */
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uint32_t sec_range0_end;
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uint32_t sec_range_enable;
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uint32_t reserved4;
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uint32_t int_pol_ctl[8]; /* 0x620 */
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uint32_t aclken_div; /* 0x640 */
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uint32_t pclken_div;
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uint32_t l2c_sram_ctrl;
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uint32_t armpll_jit_ctrl;
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uint32_t cci_addrmap; /* 0x650 */
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uint32_t cci_config;
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uint32_t cci_periphbase;
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uint32_t cci_nevntcntovfl;
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uint32_t cci_clk_ctrl; /* 0x660 */
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uint32_t cci_acel_s1_ctrl;
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uint32_t bus_fabric_dcm_ctrl;
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uint32_t reserved5;
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uint32_t xgpt_ctl; /* 0x670 */
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uint32_t xgpt_idx;
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uint32_t ptpod2_ctl0;
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uint32_t ptpod2_ctl1;
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uint32_t mcusys_revid;
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uint32_t mcusys_rw_rsvd0;
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uint32_t mcusys_rw_rsvd1;
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};
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static struct mt8173_mcucfg_regs *const mt8173_mcucfg = (void *)MCUCFG_BASE;
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/* cpu boot mode */
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#define MP0_CPUCFG_64BIT_SHIFT 12
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#define MP1_CPUCFG_64BIT_SHIFT 28
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#define MP0_CPUCFG_64BIT (U(0xf) << MP0_CPUCFG_64BIT_SHIFT)
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#define MP1_CPUCFG_64BIT (U(0xf) << MP1_CPUCFG_64BIT_SHIFT)
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/* scu related */
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enum {
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MP0_ACINACTM_SHIFT = 4,
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MP1_ACINACTM_SHIFT = 0,
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MP0_ACINACTM = 1 << MP0_ACINACTM_SHIFT,
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MP1_ACINACTM = 1 << MP1_ACINACTM_SHIFT
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};
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enum {
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MP1_DIS_RGU0_WAIT_PD_CPUS_L1_ACK_SHIFT = 0,
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MP1_DIS_RGU1_WAIT_PD_CPUS_L1_ACK_SHIFT = 4,
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MP1_DIS_RGU2_WAIT_PD_CPUS_L1_ACK_SHIFT = 8,
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MP1_DIS_RGU3_WAIT_PD_CPUS_L1_ACK_SHIFT = 12,
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MP1_DIS_RGU_NOCPU_WAIT_PD_CPUS_L1_ACK_SHIFT = 16,
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MP1_DIS_RGU0_WAIT_PD_CPUS_L1_ACK =
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0xf << MP1_DIS_RGU0_WAIT_PD_CPUS_L1_ACK_SHIFT,
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MP1_DIS_RGU1_WAIT_PD_CPUS_L1_ACK =
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0xf << MP1_DIS_RGU1_WAIT_PD_CPUS_L1_ACK_SHIFT,
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MP1_DIS_RGU2_WAIT_PD_CPUS_L1_ACK =
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0xf << MP1_DIS_RGU2_WAIT_PD_CPUS_L1_ACK_SHIFT,
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MP1_DIS_RGU3_WAIT_PD_CPUS_L1_ACK =
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0xf << MP1_DIS_RGU3_WAIT_PD_CPUS_L1_ACK_SHIFT,
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MP1_DIS_RGU_NOCPU_WAIT_PD_CPUS_L1_ACK =
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0xf << MP1_DIS_RGU_NOCPU_WAIT_PD_CPUS_L1_ACK_SHIFT
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};
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enum {
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MP1_AINACTS_SHIFT = 4,
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MP1_AINACTS = 1 << MP1_AINACTS_SHIFT
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};
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enum {
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MP1_SW_CG_GEN_SHIFT = 12,
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MP1_SW_CG_GEN = 1 << MP1_SW_CG_GEN_SHIFT
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};
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enum {
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MP1_L2RSTDISABLE_SHIFT = 14,
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MP1_L2RSTDISABLE = 1 << MP1_L2RSTDISABLE_SHIFT
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};
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/* cci clock control related */
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enum {
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MCU_BUS_DCM_EN = 1 << 8
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};
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/* l2c sram control related */
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enum {
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L2C_SRAM_DCM_EN = 1 << 0
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};
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/* bus fabric dcm control related */
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enum {
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PSYS_ADB400_DCM_EN = 1 << 29,
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GPU_ADB400_DCM_EN = 1 << 28,
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EMI1_ADB400_DCM_EN = 1 << 27,
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EMI_ADB400_DCM_EN = 1 << 26,
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INFRA_ADB400_DCM_EN = 1 << 25,
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L2C_ADB400_DCM_EN = 1 << 24,
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MP0_ADB400_DCM_EN = 1 << 23,
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CCI400_CK_ONLY_DCM_EN = 1 << 22,
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L2C_IDLE_DCM_EN = 1 << 21,
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CA15U_ADB_DYNAMIC_CG_EN = 1 << 19,
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CA7L_ADB_DYNAMIC_CG_EN = 1 << 18,
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L2C_ADB_DYNAMIC_CG_EN = 1 << 17,
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EMICLK_EMI1_DYNAMIC_CG_EN = 1 << 12,
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INFRACLK_PSYS_DYNAMIC_CG_EN = 1 << 11,
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EMICLK_GPU_DYNAMIC_CG_EN = 1 << 10,
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EMICLK_EMI_DYNAMIC_CG_EN = 1 << 8,
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CCI400_SLV_RW_DCM_EN = 1 << 7,
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CCI400_SLV_DCM_EN = 1 << 5,
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ACLK_PSYS_DYNAMIC_CG_EN = 1 << 3,
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ACLK_GPU_DYNAMIC_CG_EN = 1 << 2,
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ACLK_EMI_DYNAMIC_CG_EN = 1 << 1,
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ACLK_INFRA_DYNAMIC_CG_EN = 1 << 0,
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/* adb400 related */
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ADB400_GRP_DCM_EN = PSYS_ADB400_DCM_EN | GPU_ADB400_DCM_EN |
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EMI1_ADB400_DCM_EN | EMI_ADB400_DCM_EN |
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INFRA_ADB400_DCM_EN | L2C_ADB400_DCM_EN |
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MP0_ADB400_DCM_EN,
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/* cci400 related */
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CCI400_GRP_DCM_EN = CCI400_CK_ONLY_DCM_EN | CCI400_SLV_RW_DCM_EN |
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CCI400_SLV_DCM_EN,
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/* adb clock related */
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ADBCLK_GRP_DCM_EN = CA15U_ADB_DYNAMIC_CG_EN | CA7L_ADB_DYNAMIC_CG_EN |
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L2C_ADB_DYNAMIC_CG_EN,
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/* emi clock related */
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EMICLK_GRP_DCM_EN = EMICLK_EMI1_DYNAMIC_CG_EN |
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EMICLK_GPU_DYNAMIC_CG_EN |
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EMICLK_EMI_DYNAMIC_CG_EN,
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/* bus clock related */
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ACLK_GRP_DCM_EN = ACLK_PSYS_DYNAMIC_CG_EN | ACLK_GPU_DYNAMIC_CG_EN |
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ACLK_EMI_DYNAMIC_CG_EN | ACLK_INFRA_DYNAMIC_CG_EN,
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};
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#endif /* MCUCFG_H */
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