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3374752fc1
We plan to put some soc related drivers in common/drivers. To reduce confision, we move them to plat/mediatek. Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: I6b344e660f40a23b15151aab073d3045b28f52aa
39 lines
1.2 KiB
C
39 lines
1.2 KiB
C
/*
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* Copyright (c) 2015-2022, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef UART8250_H
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#define UART8250_H
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/* UART register */
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#define UART_RBR 0x00 /* Receive buffer register */
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#define UART_DLL 0x00 /* Divisor latch lsb */
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#define UART_THR 0x00 /* Transmit holding register */
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#define UART_DLH 0x04 /* Divisor latch msb */
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#define UART_IER 0x04 /* Interrupt enable register */
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#define UART_FCR 0x08 /* FIFO control register */
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#define UART_LCR 0x0c /* Line control register */
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#define UART_MCR 0x10 /* Modem control register */
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#define UART_LSR 0x14 /* Line status register */
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#define UART_HIGHSPEED 0x24 /* High speed UART */
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/* FCR */
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#define UART_FCR_FIFO_EN 0x01 /* enable FIFO */
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#define UART_FCR_CLEAR_RCVR 0x02 /* clear the RCVR FIFO */
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#define UART_FCR_CLEAR_XMIT 0x04 /* clear the XMIT FIFO */
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/* LCR */
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#define UART_LCR_WLS_8 0x03 /* 8 bit character length */
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#define UART_LCR_DLAB 0x80 /* divisor latch access bit */
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/* MCR */
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#define UART_MCR_DTR 0x01
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#define UART_MCR_RTS 0x02
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/* LSR */
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#define UART_LSR_DR 0x01 /* Data ready */
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#define UART_LSR_THRE 0x20 /* Xmit holding register empty */
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#endif /* UART8250_H */
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