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https://github.com/ARM-software/arm-trusted-firmware.git
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be457248c6
Add SiP service for multimedia & infra master to enable/disable MM & INFRA IOMMU in secure world TEST=build pass BUG=b:236339614 Signed-off-by: Chengci Xu <chengci.xu@mediatek.corp-partner.google.com> Change-Id: I4eb1fda6044cf2cb6c22c005cb2fa550906b71e9
126 lines
3.2 KiB
C
126 lines
3.2 KiB
C
/*
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* Copyright (c) 2022, MediaTek Inc. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <stddef.h>
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#include <mtk_iommu_plat.h>
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/* defination */
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/* smi larb */
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#define SMI_LARB_NON_SEC_CON(port) (0x380 + ((port) << 2))
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#define PATH_SEL_MASK (0xf0000) /* to sram (INT) */
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#define SMI_LARB_SEC_CON_INT(port) (0xf00 + ((port) << 2))
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#define SMI_LARB_SEC_CON(port) (0xf80 + ((port) << 2))
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#define MMU_MASK BIT(0)
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#define MMU_EN(en) ((!!(en)) << 0)
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#define SEC_MASK BIT(1)
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#define SEC_EN(en) ((!!(en)) << 1)
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#define DOMAIN_MASK (0x1f << 4)
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#define SMI_MMU_EN(port) (0x1 << (port))
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/* infra master */
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#define IFR_CFG_MMU_EN_MSK(r_bit) (0x3 << (r_bit))
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/* smi larb configure */
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/*
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* If multimedia security config is enabled, the SMI config register must be
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* configurated in security world.
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* And the SRAM path is also configurated here to enhance security.
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*/
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static void mtk_smi_larb_port_config_to_sram(
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const struct mtk_smi_larb_config *larb,
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uint32_t port_id)
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{
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mmio_clrbits_32(larb->base + SMI_LARB_SEC_CON_INT(port_id),
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MMU_MASK | SEC_MASK | DOMAIN_MASK);
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mmio_setbits_32(larb->base + SMI_LARB_NON_SEC_CON(port_id),
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PATH_SEL_MASK);
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}
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static void mtk_smi_port_config(const struct mtk_smi_larb_config *larb,
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uint32_t port_id, uint8_t mmu_en, uint8_t sec_en)
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{
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mmio_clrsetbits_32(larb->base + SMI_LARB_SEC_CON(port_id),
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MMU_MASK | SEC_MASK | DOMAIN_MASK,
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MMU_EN(mmu_en) | SEC_EN(sec_en));
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}
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static int mtk_smi_larb_port_config_sec(uint32_t larb_id, uint32_t mmu_en_msk)
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{
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uint32_t port_id, port_nr;
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const struct mtk_smi_larb_config *larb;
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uint32_t to_sram;
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uint8_t mmu_en;
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if (larb_id >= SMI_LARB_NUM) {
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return MTK_SIP_E_INVALID_PARAM;
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}
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larb = &g_larb_cfg[larb_id];
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port_nr = larb->port_nr;
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to_sram = larb->to_sram;
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for (port_id = 0; port_id < port_nr; port_id++) {
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if ((to_sram & BIT(port_id)) > 0U) {
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mtk_smi_larb_port_config_to_sram(larb, port_id);
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continue;
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}
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mmu_en = !!(mmu_en_msk & SMI_MMU_EN(port_id));
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mtk_smi_port_config(larb, port_id, mmu_en, 0);
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}
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return MTK_SIP_E_SUCCESS;
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}
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static int mtk_infra_master_config_sec(uint32_t dev_id, uint32_t enable)
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{
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const struct mtk_ifr_mst_config *ifr_cfg;
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uint32_t reg_addr;
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mtk_infra_iommu_enable_protect();
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if (dev_id >= MMU_DEV_NUM) {
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return MTK_SIP_E_NOT_SUPPORTED;
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}
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ifr_cfg = &g_ifr_mst_cfg[dev_id];
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reg_addr = g_ifr_mst_cfg_base[(ifr_cfg->cfg_addr_idx)] +
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g_ifr_mst_cfg_offs[(ifr_cfg->cfg_addr_idx)];
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if (enable > 0U) {
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mmio_setbits_32(reg_addr, IFR_CFG_MMU_EN_MSK(ifr_cfg->r_mmu_en_bit));
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} else {
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mmio_clrbits_32(reg_addr, IFR_CFG_MMU_EN_MSK(ifr_cfg->r_mmu_en_bit));
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}
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return MTK_SIP_E_SUCCESS;
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}
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static u_register_t mtk_iommu_handler(u_register_t x1, u_register_t x2,
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u_register_t x3, u_register_t x4,
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void *handle, struct smccc_res *smccc_ret)
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{
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uint32_t cmd_id = x1, mdl_id = x2, val = x3;
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int ret = MTK_SIP_E_NOT_SUPPORTED;
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(void)x4;
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(void)handle;
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switch (cmd_id) {
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case IOMMU_ATF_CMD_CONFIG_SMI_LARB:
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ret = mtk_smi_larb_port_config_sec(mdl_id, val);
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break;
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case IOMMU_ATF_CMD_CONFIG_INFRA_IOMMU:
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ret = mtk_infra_master_config_sec(mdl_id, val);
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break;
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default:
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break;
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}
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return ret;
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}
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DECLARE_SMC_HANDLER(MTK_SIP_IOMMU_CONTROL, mtk_iommu_handler);
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