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https://github.com/ARM-software/arm-trusted-firmware.git
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7079a942bd
DFD (Design for Debug) is a debugging tool, which scans flip-flops and dumps to internal RAM on the WDT reset. After system reboots, those values could be showed for debugging. TEST=build pass. BUG=b:244216434 Signed-off-by: Fengquan Chen <fengquan.chen@mediatek.corp-partner.google.com> Change-Id: I468036131e941a46bc1ec12d33105146000730d8
83 lines
2.5 KiB
C
83 lines
2.5 KiB
C
/*
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* Copyright (c) 2022, MediaTek Inc. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch_helpers.h>
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#include <common/debug.h>
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#include <lib/mmio.h>
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#include <dfd.h>
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#include <plat_dfd.h>
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static uint64_t dfd_cache_dump;
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static bool dfd_enabled;
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static uint64_t dfd_base_addr;
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static uint64_t dfd_chain_length;
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void dfd_setup(uint64_t base_addr, uint64_t chain_length, uint64_t cache_dump)
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{
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mmio_write_32(MTK_DRM_LATCH_CTL1, MTK_DRM_LATCH_CTL1_VAL);
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mmio_write_32(MTK_DRM_LATCH_CTL2, MTK_DRM_LATCH_CTL2_VAL);
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mmio_write_32(MTK_WDT_LATCH_CTL2, MTK_WDT_LATCH_CTL2_VAL);
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mmio_clrbits_32(DFD_O_INTRF_MCU_PWR_CTL_MASK, BIT(2));
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mmio_setbits_32(DFD_V50_GROUP_0_63_DIFF, 0x1);
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sync_writel(DFD_INTERNAL_CTL, 0x5);
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mmio_setbits_32(DFD_INTERNAL_CTL, BIT(13));
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mmio_setbits_32(DFD_INTERNAL_CTL, 0x1F << 3);
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mmio_setbits_32(DFD_INTERNAL_CTL, 0x3 << 9);
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mmio_setbits_32(DFD_INTERNAL_CTL, 0x3 << 19);
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mmio_write_32(DFD_INTERNAL_PWR_ON, 0xB);
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mmio_write_32(DFD_CHAIN_LENGTH0, chain_length);
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mmio_write_32(DFD_INTERNAL_SHIFT_CLK_RATIO, 0x0);
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mmio_write_32(DFD_INTERNAL_TEST_SO_OVER_64, 0x1);
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mmio_write_32(DFD_TEST_SI_0, 0x0);
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mmio_write_32(DFD_TEST_SI_1, 0x0);
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mmio_write_32(DFD_TEST_SI_2, 0x0);
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mmio_write_32(DFD_TEST_SI_3, 0x0);
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sync_writel(DFD_POWER_CTL, 0xF9);
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sync_writel(DFD_READ_ADDR, DFD_READ_ADDR_VAL);
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sync_writel(DFD_V30_CTL, 0xD);
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mmio_write_32(DFD_O_SET_BASEADDR_REG, base_addr >> 24);
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mmio_write_32(DFD_O_REG_0, 0);
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/* setup global variables for suspend and resume */
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dfd_enabled = true;
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dfd_base_addr = base_addr;
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dfd_chain_length = chain_length;
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dfd_cache_dump = cache_dump;
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if ((cache_dump & DFD_CACHE_DUMP_ENABLE) != 0UL) {
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mmio_write_32(MTK_DRM_LATCH_CTL2, MTK_DRM_LATCH_CTL2_CACHE_VAL);
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sync_writel(DFD_V35_ENABLE, 0x1);
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sync_writel(DFD_V35_TAP_NUMBER, 0xB);
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sync_writel(DFD_V35_TAP_EN, DFD_V35_TAP_EN_VAL);
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sync_writel(DFD_V35_SEQ0_0, DFD_V35_SEQ0_0_VAL);
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/* Cache dump only mode */
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sync_writel(DFD_V35_CTL, 0x1);
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mmio_write_32(DFD_INTERNAL_NUM_OF_TEST_SO_GROUP, 0xF);
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mmio_write_32(DFD_CHAIN_LENGTH0, DFD_CHAIN_LENGTH_VAL);
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mmio_write_32(DFD_CHAIN_LENGTH1, DFD_CHAIN_LENGTH_VAL);
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mmio_write_32(DFD_CHAIN_LENGTH2, DFD_CHAIN_LENGTH_VAL);
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mmio_write_32(DFD_CHAIN_LENGTH3, DFD_CHAIN_LENGTH_VAL);
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if ((cache_dump & DFD_PARITY_ERR_TRIGGER) != 0UL) {
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sync_writel(DFD_HW_TRIGGER_MASK, 0xC);
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mmio_setbits_32(DFD_INTERNAL_CTL, 0x1 << 4);
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}
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}
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dsbsy();
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}
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void dfd_resume(void)
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{
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if (dfd_enabled == true) {
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dfd_setup(dfd_base_addr, dfd_chain_length, dfd_cache_dump);
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}
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}
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