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bc9410e237
DCM means dynamic clock management, and it can dynamically slow down or gate clocks during CPU or bus idle. 1. Add MCUSYS related DCM drivers. 2. Enable MCUSYS related DCM by default. Signed-off-by: Garmin Chang <garmin.chang@mediatek.com> Change-Id: I131354d72bbc190af504e9639bcc85a720e2bb17
85 lines
1.9 KiB
C
85 lines
1.9 KiB
C
/*
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* Copyright (c) 2022, MediaTek Inc. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <common/debug.h>
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#include <lib/mmio.h>
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#include <lib/mtk_init/mtk_init.h>
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#include <mtk_dcm.h>
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#include <mtk_dcm_utils.h>
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static void dcm_armcore(bool mode)
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{
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dcm_mp_cpusys_top_bus_pll_div_dcm(mode);
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dcm_mp_cpusys_top_cpu_pll_div_0_dcm(mode);
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dcm_mp_cpusys_top_cpu_pll_div_1_dcm(mode);
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}
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static void dcm_mcusys(bool on)
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{
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dcm_mp_cpusys_top_adb_dcm(on);
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dcm_mp_cpusys_top_apb_dcm(on);
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dcm_mp_cpusys_top_cpubiu_dcm(on);
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dcm_mp_cpusys_top_misc_dcm(on);
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dcm_mp_cpusys_top_mp0_qdcm(on);
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/* CPCCFG_REG */
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dcm_cpccfg_reg_emi_wfifo(on);
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dcm_mp_cpusys_top_last_cor_idle_dcm(on);
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}
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static void dcm_stall(bool on)
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{
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dcm_mp_cpusys_top_core_stall_dcm(on);
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dcm_mp_cpusys_top_fcm_stall_dcm(on);
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}
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static bool check_dcm_state(void)
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{
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bool ret = true;
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ret &= dcm_mp_cpusys_top_bus_pll_div_dcm_is_on();
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ret &= dcm_mp_cpusys_top_cpu_pll_div_0_dcm_is_on();
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ret &= dcm_mp_cpusys_top_cpu_pll_div_1_dcm_is_on();
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ret &= dcm_mp_cpusys_top_adb_dcm_is_on();
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ret &= dcm_mp_cpusys_top_apb_dcm_is_on();
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ret &= dcm_mp_cpusys_top_cpubiu_dcm_is_on();
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ret &= dcm_mp_cpusys_top_misc_dcm_is_on();
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ret &= dcm_mp_cpusys_top_mp0_qdcm_is_on();
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ret &= dcm_cpccfg_reg_emi_wfifo_is_on();
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ret &= dcm_mp_cpusys_top_last_cor_idle_dcm_is_on();
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ret &= dcm_mp_cpusys_top_core_stall_dcm_is_on();
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ret &= dcm_mp_cpusys_top_fcm_stall_dcm_is_on();
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return ret;
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}
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bool dcm_check_state(uintptr_t addr, unsigned int mask, unsigned int compare)
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{
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return ((mmio_read_32(addr) & mask) == compare);
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}
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int dcm_set_init(void)
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{
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int ret;
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dcm_armcore(true);
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dcm_mcusys(true);
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dcm_stall(true);
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if (check_dcm_state() == false) {
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ERROR("Failed to set default dcm on!!\n");
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ret = -1;
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} else {
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INFO("%s, dcm pass\n", __func__);
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ret = 0;
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}
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return ret;
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}
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MTK_PLAT_SETUP_0_INIT(dcm_set_init);
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