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57870747e2
The CP MSS IRAM is only accessible by CM3 CPU and MSS DMA. In secure boot mode the MSS DMA is unable to directly load the MSS FW image from DRAM to IRAM. This patch adds support for using the MSS SRAM as intermediate storage. The MSS FW image is loaded by application CPU into the MSS SRAM first, then transferred to MSS IRAM by MSS DMA. Such change allows the CP MSS image load in secure mode. Change-Id: Iee7a51d157743a0bdf8acb668ee3d599f760a712 Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Reviewed-by: Stefan Chulski <stefanc@marvell.com> Reviewed-by: Grzegorz Jaszczyk <jaszczyk@marvell.com>
21 lines
644 B
C
21 lines
644 B
C
/*
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* Copyright (C) 2018 Marvell International Ltd.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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* https://spdx.org/licenses
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*/
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#ifndef MSS_SCP_BOOTLOADER_H
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#define MSS_SCP_BOOTLOADER_H
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int scp_bootloader_transfer(void *image, unsigned int image_size);
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uintptr_t bl2_plat_get_cp_mss_regs(int ap_idx, int cp_idx);
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uintptr_t bl2_plat_get_cp_mss_sram(int ap_idx, int cp_idx);
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uintptr_t bl2_plat_get_ap_mss_regs(int ap_idx);
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uint32_t bl2_plat_get_cp_count(int ap_idx);
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uint32_t bl2_plat_get_ap_count(void);
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void bl2_plat_configure_mss_windows(uintptr_t mss_regs);
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int bl2_plat_mss_check_image_ready(void);
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#endif /* MSS_SCP_BOOTLOADER_H */
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