mirror of
https://github.com/ARM-software/arm-trusted-firmware.git
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a28471722a
This commit is a preparation for upcoming support for OcteonTX and OcteonTX2 product families. Armada platform related files (docs, plat, include/plat) are moved to the new "armada" sub-folder. Change-Id: Icf03356187078ad6a2e56c9870992be3ca4c9655 Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> Signed-off-by: Marcin Wojtas <mw@semihalf.com>
61 lines
1.4 KiB
C
61 lines
1.4 KiB
C
/*
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* Copyright (C) 2018 Marvell International Ltd.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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* https://spdx.org/licenses
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*/
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#ifndef MSS_MEM_H
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#define MSS_MEM_H
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/* MSS SRAM Memory base */
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#define MSS_SRAM_PM_CONTROL_BASE (MVEBU_REGS_BASE + 0x520000)
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enum mss_pm_ctrl_handshake {
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MSS_UN_INITIALIZED = 0,
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MSS_COMPATIBILITY_ERROR = 1,
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MSS_ACKNOWLEDGMENT = 2,
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HOST_ACKNOWLEDGMENT = 3
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};
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enum mss_pm_ctrl_rtos_env {
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MSS_MULTI_PROCESS_ENV = 0,
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MSS_SINGLE_PROCESS_ENV = 1,
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MSS_MAX_PROCESS_ENV
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};
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struct mss_pm_ctrl_block {
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/* This field is used to synchronize the Host
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* and MSS initialization sequence
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* Valid Values
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* 0 - Un-Initialized
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* 1 - Compatibility Error
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* 2 - MSS Acknowledgment
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* 3 - Host Acknowledgment
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*/
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unsigned int handshake;
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/*
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* This field include Host IPC version. Once received by the MSS
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* It will be compared to MSS IPC version and set MSS Acknowledge to
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* "compatibility error" in case there is no match
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*/
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unsigned int ipc_version;
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unsigned int ipc_base_address;
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unsigned int ipc_state;
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/* Following fields defines firmware core architecture */
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unsigned int num_of_cores;
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unsigned int num_of_clusters;
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unsigned int num_of_cores_per_cluster;
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/* Following fields define pm trace debug base address */
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unsigned int pm_trace_ctrl_base_address;
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unsigned int pm_trace_info_base_address;
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unsigned int pm_trace_info_core_size;
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unsigned int ctrl_blk_size;
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};
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#endif /* MSS_MEM_H */
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