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718dbcac9c
Setting MSS_SUPPORT to 0 also removes requirement for SCP_BL2 definition. Images build with MSS_SUPPORT=0 will not include service CPUs FW and will not support PM, FC and other features implemented in these FW images. Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Change-Id: Idf301ebd218ce65a60f277f3876d0aeb6c72f105 Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/boot/atf/+/37769 Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com> Reviewed-by: Stefan Chulski <stefanc@marvell.com> Reviewed-by: Ofer Heifetz <oferh@marvell.com> Reviewed-by: Nadav Haklai <nadavh@marvell.com>
95 lines
2.9 KiB
C
95 lines
2.9 KiB
C
/*
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* Copyright (C) 2018 Marvell International Ltd.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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* https://spdx.org/licenses
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*/
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#include <lib/mmio.h>
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#include <plat/common/platform.h>
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#if MSS_SUPPORT
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#include <mss_mem.h>
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#ifdef PM_TRACE_ENABLE
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#include <plat_pm_trace.h>
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/* core trace APIs */
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core_trace_func funcTbl[PLATFORM_CORE_COUNT] = {
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pm_core_0_trace,
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pm_core_1_trace,
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pm_core_2_trace,
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pm_core_3_trace};
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/*****************************************************************************
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* pm_core0_trace
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* pm_core1_trace
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* pm_core2_trace
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* pm_core_3trace
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*
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* This functions set trace info into core cyclic trace queue in MSS SRAM
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* memory space
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*****************************************************************************
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*/
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void pm_core_0_trace(unsigned int trace)
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{
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unsigned int current_position_core_0 =
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mmio_read_32(AP_MSS_ATF_CORE_0_CTRL_BASE);
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mmio_write_32((AP_MSS_ATF_CORE_0_INFO_BASE +
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(current_position_core_0 * AP_MSS_ATF_CORE_ENTRY_SIZE)),
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mmio_read_32(AP_MSS_TIMER_BASE));
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mmio_write_32((AP_MSS_ATF_CORE_0_INFO_TRACE +
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(current_position_core_0 * AP_MSS_ATF_CORE_ENTRY_SIZE)),
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trace);
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mmio_write_32(AP_MSS_ATF_CORE_0_CTRL_BASE,
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((current_position_core_0 + 1) &
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AP_MSS_ATF_TRACE_SIZE_MASK));
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}
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void pm_core_1_trace(unsigned int trace)
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{
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unsigned int current_position_core_1 =
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mmio_read_32(AP_MSS_ATF_CORE_1_CTRL_BASE);
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mmio_write_32((AP_MSS_ATF_CORE_1_INFO_BASE +
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(current_position_core_1 * AP_MSS_ATF_CORE_ENTRY_SIZE)),
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mmio_read_32(AP_MSS_TIMER_BASE));
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mmio_write_32((AP_MSS_ATF_CORE_1_INFO_TRACE +
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(current_position_core_1 * AP_MSS_ATF_CORE_ENTRY_SIZE)),
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trace);
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mmio_write_32(AP_MSS_ATF_CORE_1_CTRL_BASE,
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((current_position_core_1 + 1) &
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AP_MSS_ATF_TRACE_SIZE_MASK));
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}
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void pm_core_2_trace(unsigned int trace)
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{
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unsigned int current_position_core_2 =
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mmio_read_32(AP_MSS_ATF_CORE_2_CTRL_BASE);
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mmio_write_32((AP_MSS_ATF_CORE_2_INFO_BASE +
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(current_position_core_2 * AP_MSS_ATF_CORE_ENTRY_SIZE)),
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mmio_read_32(AP_MSS_TIMER_BASE));
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mmio_write_32((AP_MSS_ATF_CORE_2_INFO_TRACE +
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(current_position_core_2 * AP_MSS_ATF_CORE_ENTRY_SIZE)),
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trace);
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mmio_write_32(AP_MSS_ATF_CORE_2_CTRL_BASE,
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((current_position_core_2 + 1) &
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AP_MSS_ATF_TRACE_SIZE_MASK));
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}
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void pm_core_3_trace(unsigned int trace)
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{
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unsigned int current_position_core_3 =
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mmio_read_32(AP_MSS_ATF_CORE_3_CTRL_BASE);
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mmio_write_32((AP_MSS_ATF_CORE_3_INFO_BASE +
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(current_position_core_3 * AP_MSS_ATF_CORE_ENTRY_SIZE)),
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mmio_read_32(AP_MSS_TIMER_BASE));
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mmio_write_32((AP_MSS_ATF_CORE_3_INFO_TRACE +
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(current_position_core_3 * AP_MSS_ATF_CORE_ENTRY_SIZE)),
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trace);
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mmio_write_32(AP_MSS_ATF_CORE_3_CTRL_BASE,
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((current_position_core_3 + 1) &
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AP_MSS_ATF_TRACE_SIZE_MASK));
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}
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#endif /* PM_TRACE_ENABLE */
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#endif /* MSS_SUPPORT */
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