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https://github.com/ARM-software/arm-trusted-firmware.git
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b5a0663771
Normally the CP MSS CPU was started at the end of FW load to IRAM at BL2. However, (especailly in secure boot mode), some bus attributes should be changed from defaults before the MSS CPU tries to access shared resources. This patch starts to use CP MSS SRAM for FW load in both secure and non-secure boot modes. The FW loader inserts a magic number into MSS SRAM as an indicator of successfully loaded FS during the BL2 stage and skips releasing the MSS CPU from the reset state. Then, at BL31 stage, the MSS CPU is released from reset following the call to cp110_init function that handles all the required bus attributes configurations. Change-Id: Idcf81cc350a086835abed365154051dd79f1ce2e Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/boot/atf/+/46890 Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com>
149 lines
3.5 KiB
C
149 lines
3.5 KiB
C
/*
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* Copyright (C) 2018 Marvell International Ltd.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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* https://spdx.org/licenses
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*/
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#include <common/debug.h>
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#include <drivers/marvell/mci.h>
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#include <drivers/marvell/mochi/ap_setup.h>
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#include <drivers/marvell/mochi/cp110_setup.h>
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#include <lib/mmio.h>
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#include <armada_common.h>
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#include <marvell_plat_priv.h>
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#include <marvell_pm.h>
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#include <mc_trustzone/mc_trustzone.h>
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#include <plat_marvell.h>
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#if MSS_SUPPORT
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#include <mss_ipc_drv.h>
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#include <mss_mem.h>
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#include <mss_defs.h>
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#endif
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/* In Armada-8k family AP806/AP807, CP0 connected to PIDI
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* and CP1 connected to IHB via MCI #0
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*/
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#define MVEBU_MCI0 0
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static _Bool pm_fw_running;
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/* Set a weak stub for platforms that don't need to configure GPIO */
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#pragma weak marvell_gpio_config
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int marvell_gpio_config(void)
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{
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return 0;
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}
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static void marvell_bl31_mpp_init(int cp)
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{
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uint32_t reg;
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/* need to do for CP#0 only */
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if (cp)
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return;
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/*
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* Enable CP0 I2C MPPs (MPP: 37-38)
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* U-Boot rely on proper MPP settings for I2C EEPROM usage
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* (only for CP0)
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*/
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reg = mmio_read_32(MVEBU_CP_MPP_REGS(0, 4));
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mmio_write_32(MVEBU_CP_MPP_REGS(0, 4), reg | 0x2200000);
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}
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#if MSS_SUPPORT
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void marvell_bl31_mss_init(void)
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{
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struct mss_pm_ctrl_block *mss_pm_crtl =
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(struct mss_pm_ctrl_block *)MSS_SRAM_PM_CONTROL_BASE;
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/* Check that the image was loaded successfully */
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if (mss_pm_crtl->handshake != HOST_ACKNOWLEDGMENT) {
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NOTICE("MSS PM is not supported in this build\n");
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return;
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}
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/* If we got here it means that the PM firmware is running */
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pm_fw_running = 1;
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INFO("MSS IPC init\n");
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if (mss_pm_crtl->ipc_state == IPC_INITIALIZED)
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mv_pm_ipc_init(mss_pm_crtl->ipc_base_address | MVEBU_REGS_BASE);
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}
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#endif
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_Bool is_pm_fw_running(void)
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{
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return pm_fw_running;
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}
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/* For TrusTzone we treat the "target" field of addr_map_win
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* struct as attribute
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*/
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static const struct addr_map_win tz_map[] = {
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{PLAT_MARVELL_ATF_BASE, 0x200000, TZ_PERM_ABORT}
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};
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/* Configure MC TrustZone regions */
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static void marvell_bl31_security_setup(void)
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{
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int tz_nr, win_id;
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tz_nr = ARRAY_SIZE(tz_map);
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for (win_id = 0; win_id < tz_nr; win_id++)
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tz_enable_win(MVEBU_AP0, tz_map, win_id);
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}
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/* This function overruns the same function in marvell_bl31_setup.c */
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void bl31_plat_arch_setup(void)
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{
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int cp;
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uintptr_t *mailbox = (void *)PLAT_MARVELL_MAILBOX_BASE;
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/* initialize the timer for mdelay/udelay functionality */
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plat_delay_timer_init();
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/* configure apn806 */
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ap_init();
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/* In marvell_bl31_plat_arch_setup, el3 mmu is configured.
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* el3 mmu configuration MUST be called after apn806_init, if not,
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* this will cause an hang in init_io_win
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* (after setting the IO windows GCR values).
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*/
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if (mailbox[MBOX_IDX_MAGIC] != MVEBU_MAILBOX_MAGIC_NUM ||
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mailbox[MBOX_IDX_SUSPEND_MAGIC] != MVEBU_MAILBOX_SUSPEND_STATE)
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marvell_bl31_plat_arch_setup();
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for (cp = 0; cp < CP_COUNT; cp++) {
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cp110_init(MVEBU_CP_REGS_BASE(cp),
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STREAM_ID_BASE + (cp * MAX_STREAM_ID_PER_CP));
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marvell_bl31_mpp_init(cp);
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#if MSS_SUPPORT
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/* Release CP MSS CPU from reset once the CP init is done */
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mss_start_cp_cm3(cp);
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#endif
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}
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for (cp = 1; cp < CP_COUNT; cp++)
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mci_link_tune(cp - 1);
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#if MSS_SUPPORT
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/* initialize IPC between MSS and ATF */
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if (mailbox[MBOX_IDX_MAGIC] != MVEBU_MAILBOX_MAGIC_NUM ||
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mailbox[MBOX_IDX_SUSPEND_MAGIC] != MVEBU_MAILBOX_SUSPEND_STATE)
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marvell_bl31_mss_init();
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#endif
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/* Configure GPIO */
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marvell_gpio_config();
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marvell_bl31_security_setup();
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}
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