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b5a0663771
Normally the CP MSS CPU was started at the end of FW load to IRAM at BL2. However, (especailly in secure boot mode), some bus attributes should be changed from defaults before the MSS CPU tries to access shared resources. This patch starts to use CP MSS SRAM for FW load in both secure and non-secure boot modes. The FW loader inserts a magic number into MSS SRAM as an indicator of successfully loaded FS during the BL2 stage and skips releasing the MSS CPU from the reset state. Then, at BL31 stage, the MSS CPU is released from reset following the call to cp110_init function that handles all the required bus attributes configurations. Change-Id: Idcf81cc350a086835abed365154051dd79f1ce2e Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/boot/atf/+/46890 Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com>
34 lines
866 B
C
34 lines
866 B
C
/*
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* Copyright (C) 2021 Marvell International Ltd.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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* https://spdx.org/licenses
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*/
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#ifndef MSS_DEFS_H
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#define MSS_DEFS_H
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#define MSS_DMA_SRCBR(base) (base + 0xC0)
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#define MSS_DMA_DSTBR(base) (base + 0xC4)
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#define MSS_DMA_CTRLR(base) (base + 0xC8)
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#define MSS_M3_RSTCR(base) (base + 0xFC)
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#define MSS_DMA_CTRLR_SIZE_OFFSET (0)
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#define MSS_DMA_CTRLR_REQ_OFFSET (15)
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#define MSS_DMA_CTRLR_REQ_SET (1)
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#define MSS_DMA_CTRLR_ACK_OFFSET (12)
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#define MSS_DMA_CTRLR_ACK_MASK (0x1)
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#define MSS_DMA_CTRLR_ACK_READY (1)
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#define MSS_M3_RSTCR_RST_OFFSET (0)
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#define MSS_M3_RSTCR_RST_OFF (1)
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#define MSS_FW_READY_MAGIC 0x46575144 /* FWRD */
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#define MSS_AP_REGS_OFFSET 0x00580000
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#define MSS_CP_SRAM_OFFSET 0x00220000
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#define MSS_CP_REGS_OFFSET 0x00280000
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void mss_start_cp_cm3(int cp);
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#endif /* MSS_DEFS_H */
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