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9c336f6118
Add the DDR frequency change support. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Change-Id: If1167785796b8678c351569b83d2922c66f6e530
79 lines
1.8 KiB
C
79 lines
1.8 KiB
C
/*
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* Copyright 2019-2022 NXP
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef DRAM_H
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#define DRAM_H
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#include <assert.h>
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#include <arch_helpers.h>
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#include <lib/utils_def.h>
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#include <ddrc.h>
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#include <platform_def.h>
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#define DDRC_LPDDR4 BIT(5)
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#define DDRC_DDR4 BIT(4)
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#define DDRC_DDR3L BIT(0)
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#define DDR_TYPE_MASK U(0x3f)
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#define ACTIVE_RANK_MASK U(0x3)
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/* reg & config param */
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struct dram_cfg_param {
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unsigned int reg;
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unsigned int val;
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};
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struct dram_timing_info {
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/* umctl2 config */
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struct dram_cfg_param *ddrc_cfg;
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unsigned int ddrc_cfg_num;
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/* ddrphy config */
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struct dram_cfg_param *ddrphy_cfg;
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unsigned int ddrphy_cfg_num;
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/* ddr fsp train info */
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struct dram_fsp_msg *fsp_msg;
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unsigned int fsp_msg_num;
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/* ddr phy trained CSR */
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struct dram_cfg_param *ddrphy_trained_csr;
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unsigned int ddrphy_trained_csr_num;
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/* ddr phy PIE */
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struct dram_cfg_param *ddrphy_pie;
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unsigned int ddrphy_pie_num;
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/* initialized fsp table */
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unsigned int fsp_table[4];
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};
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struct dram_info {
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int dram_type;
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unsigned int num_rank;
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uint32_t num_fsp;
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int current_fsp;
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int boot_fsp;
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bool bypass_mode;
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struct dram_timing_info *timing_info;
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/* mr, emr, emr2, emr3, mr11, mr12, mr22, mr14 */
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uint32_t mr_table[3][8];
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};
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extern struct dram_info dram_info;
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void dram_info_init(unsigned long dram_timing_base);
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void dram_umctl2_init(struct dram_timing_info *timing);
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void dram_phy_init(struct dram_timing_info *timing);
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/* dram retention */
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void dram_enter_retention(void);
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void dram_exit_retention(void);
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void dram_clock_switch(unsigned int target_drate, bool bypass_mode);
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/* dram frequency change */
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void lpddr4_swffc(struct dram_info *info, unsigned int init_fsp, unsigned int fsp_index);
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void ddr4_swffc(struct dram_info *dram_info, unsigned int pstate);
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#endif /* DRAM_H */
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