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https://github.com/ARM-software/arm-trusted-firmware.git
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cfde1870ca
On Hikey960 if outputs GPIO176 low level, it can tell PMIC to power off the whole board. To avoid resetting the board and stay off, it also requires the SW2201's three switches 1/2/3 need to be all set to 0. Since current code doesn't contain complete GPIO modules and misses to support GPIO176. This patch adds all known GPIO modules and initialize GPIO in BL31, and adds system power off callback to use GPIO176 for PMIC power off operation. Change-Id: Ia88859b8b7c87c061420ef75f0de3e2768667bb0 Signed-off-by: Leo Yan <leo.yan@linaro.org>
338 lines
8.1 KiB
C
338 lines
8.1 KiB
C
/*
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* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <arch_helpers.h>
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#include <common/debug.h>
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#include <drivers/arm/cci.h>
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#include <drivers/arm/gicv2.h>
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#include <drivers/arm/pl011.h>
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#include <drivers/arm/pl061_gpio.h>
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#include <drivers/delay_timer.h>
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#include <lib/mmio.h>
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#include <lib/psci/psci.h>
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#include <hi3660.h>
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#include <hi3660_crg.h>
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#include "drivers/pwrc/hisi_pwrc.h"
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#include "hikey960_def.h"
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#include "hikey960_private.h"
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#define CORE_PWR_STATE(state) \
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((state)->pwr_domain_state[MPIDR_AFFLVL0])
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#define CLUSTER_PWR_STATE(state) \
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((state)->pwr_domain_state[MPIDR_AFFLVL1])
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#define SYSTEM_PWR_STATE(state) \
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((state)->pwr_domain_state[PLAT_MAX_PWR_LVL])
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#define DMAC_GLB_REG_SEC 0x694
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#define AXI_CONF_BASE 0x820
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static unsigned int uart_base;
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static console_t console;
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static uintptr_t hikey960_sec_entrypoint;
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static void hikey960_pwr_domain_standby(plat_local_state_t cpu_state)
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{
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unsigned long scr;
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scr = read_scr_el3();
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/* Enable Physical IRQ and FIQ to wake the CPU */
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write_scr_el3(scr | SCR_IRQ_BIT | SCR_FIQ_BIT);
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/* Add barrier before CPU enter WFI state */
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isb();
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dsb();
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wfi();
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/*
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* Restore SCR to the original value, synchronisazion of
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* scr_el3 is done by eret while el3_exit to save some
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* execution cycles.
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*/
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write_scr_el3(scr);
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}
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static int hikey960_pwr_domain_on(u_register_t mpidr)
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{
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unsigned int core = mpidr & MPIDR_CPU_MASK;
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unsigned int cluster =
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(mpidr & MPIDR_CLUSTER_MASK) >> MPIDR_AFFINITY_BITS;
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int cluster_stat = cluster_is_powered_on(cluster);
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hisi_set_cpu_boot_flag(cluster, core);
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mmio_write_32(CRG_REG_BASE + CRG_RVBAR(cluster, core),
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hikey960_sec_entrypoint >> 2);
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if (cluster_stat)
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hisi_powerup_core(cluster, core);
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else
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hisi_powerup_cluster(cluster, core);
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return PSCI_E_SUCCESS;
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}
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static void
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hikey960_pwr_domain_on_finish(const psci_power_state_t *target_state)
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{
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if (CLUSTER_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE)
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cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr_el1()));
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gicv2_pcpu_distif_init();
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gicv2_cpuif_enable();
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}
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void hikey960_pwr_domain_off(const psci_power_state_t *target_state)
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{
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unsigned long mpidr = read_mpidr_el1();
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unsigned int core = mpidr & MPIDR_CPU_MASK;
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unsigned int cluster =
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(mpidr & MPIDR_CLUSTER_MASK) >> MPIDR_AFFINITY_BITS;
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clr_ex();
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isb();
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dsbsy();
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gicv2_cpuif_disable();
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hisi_clear_cpu_boot_flag(cluster, core);
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hisi_powerdn_core(cluster, core);
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/* check if any core is powered up */
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if (hisi_test_cpu_down(cluster, core)) {
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cci_disable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr_el1()));
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isb();
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dsbsy();
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hisi_powerdn_cluster(cluster, core);
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}
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}
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static void __dead2 hikey960_system_off(void)
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{
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gpio_set_direction(176, GPIO_DIR_OUT);
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gpio_set_value(176, GPIO_LEVEL_LOW);
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panic();
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}
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static void __dead2 hikey960_system_reset(void)
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{
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dsb();
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isb();
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mdelay(2000);
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mmio_write_32(SCTRL_SCPEREN1_REG,
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SCPEREN1_WAIT_DDR_SELFREFRESH_DONE_BYPASS);
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mmio_write_32(SCTRL_SCSYSSTAT_REG, 0xdeadbeef);
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panic();
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}
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int hikey960_validate_power_state(unsigned int power_state,
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psci_power_state_t *req_state)
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{
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unsigned int pstate = psci_get_pstate_type(power_state);
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unsigned int pwr_lvl = psci_get_pstate_pwrlvl(power_state);
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int i;
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assert(req_state);
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if (pwr_lvl > PLAT_MAX_PWR_LVL)
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return PSCI_E_INVALID_PARAMS;
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/* Sanity check the requested state */
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if (pstate == PSTATE_TYPE_STANDBY) {
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/*
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* It's possible to enter standby only on power level 0
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* Ignore any other power level.
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*/
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if (pwr_lvl != MPIDR_AFFLVL0)
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return PSCI_E_INVALID_PARAMS;
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req_state->pwr_domain_state[MPIDR_AFFLVL0] =
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PLAT_MAX_RET_STATE;
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} else {
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for (i = MPIDR_AFFLVL0; i <= pwr_lvl; i++)
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req_state->pwr_domain_state[i] =
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PLAT_MAX_OFF_STATE;
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}
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/*
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* We expect the 'state id' to be zero.
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*/
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if (psci_get_pstate_id(power_state))
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return PSCI_E_INVALID_PARAMS;
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return PSCI_E_SUCCESS;
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}
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static int hikey960_validate_ns_entrypoint(uintptr_t entrypoint)
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{
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/*
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* Check if the non secure entrypoint lies within the non
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* secure DRAM.
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*/
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if ((entrypoint > DDR_BASE) && (entrypoint < (DDR_BASE + DDR_SIZE)))
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return PSCI_E_SUCCESS;
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return PSCI_E_INVALID_ADDRESS;
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}
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static void hikey960_pwr_domain_suspend(const psci_power_state_t *target_state)
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{
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u_register_t mpidr = read_mpidr_el1();
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unsigned int core = mpidr & MPIDR_CPU_MASK;
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unsigned int cluster =
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(mpidr & MPIDR_CLUSTER_MASK) >> MPIDR_AFFINITY_BITS;
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if (CORE_PWR_STATE(target_state) != PLAT_MAX_OFF_STATE)
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return;
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if (CORE_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE) {
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clr_ex();
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isb();
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dsbsy();
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gicv2_cpuif_disable();
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hisi_cpuidle_lock(cluster, core);
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hisi_set_cpuidle_flag(cluster, core);
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hisi_cpuidle_unlock(cluster, core);
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mmio_write_32(CRG_REG_BASE + CRG_RVBAR(cluster, core),
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hikey960_sec_entrypoint >> 2);
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hisi_enter_core_idle(cluster, core);
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}
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/* Perform the common cluster specific operations */
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if (CLUSTER_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE) {
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hisi_cpuidle_lock(cluster, core);
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hisi_disable_pdc(cluster);
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/* check if any core is powered up */
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if (hisi_test_pwrdn_allcores(cluster, core)) {
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cci_disable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(mpidr));
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isb();
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dsbsy();
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/* mask the pdc wakeup irq, then
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* enable pdc to power down the core
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*/
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hisi_pdc_mask_cluster_wakeirq(cluster);
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hisi_enable_pdc(cluster);
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hisi_cpuidle_unlock(cluster, core);
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/* check the SR flag bit to determine
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* CLUSTER_IDLE_IPC or AP_SR_IPC to send
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*/
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if (hisi_test_ap_suspend_flag())
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hisi_enter_ap_suspend(cluster, core);
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else
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hisi_enter_cluster_idle(cluster, core);
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} else {
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/* enable pdc */
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hisi_enable_pdc(cluster);
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hisi_cpuidle_unlock(cluster, core);
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}
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}
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}
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static void hikey960_sr_dma_reinit(void)
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{
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unsigned int ctr = 0;
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mmio_write_32(DMAC_BASE + DMAC_GLB_REG_SEC, 0x3);
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/* 1~15 channel is set non_secure */
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for (ctr = 1; ctr <= 15; ctr++)
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mmio_write_32(DMAC_BASE + AXI_CONF_BASE + ctr * (0x40),
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(1 << 6) | (1 << 18));
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}
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static void
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hikey960_pwr_domain_suspend_finish(const psci_power_state_t *target_state)
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{
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unsigned long mpidr = read_mpidr_el1();
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unsigned int core = mpidr & MPIDR_CPU_MASK;
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unsigned int cluster =
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(mpidr & MPIDR_CLUSTER_MASK) >> MPIDR_AFFINITY_BITS;
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/* Nothing to be done on waking up from retention from CPU level */
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if (CORE_PWR_STATE(target_state) != PLAT_MAX_OFF_STATE)
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return;
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hisi_cpuidle_lock(cluster, core);
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hisi_clear_cpuidle_flag(cluster, core);
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hisi_cpuidle_unlock(cluster, core);
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if (hisi_test_ap_suspend_flag()) {
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hikey960_sr_dma_reinit();
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gicv2_cpuif_enable();
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console_pl011_register(uart_base, PL011_UART_CLK_IN_HZ,
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PL011_BAUDRATE, &console);
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}
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hikey960_pwr_domain_on_finish(target_state);
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}
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static void hikey960_get_sys_suspend_power_state(psci_power_state_t *req_state)
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{
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int i;
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for (i = MPIDR_AFFLVL0; i <= PLAT_MAX_PWR_LVL; i++)
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req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE;
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}
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static const plat_psci_ops_t hikey960_psci_ops = {
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.cpu_standby = hikey960_pwr_domain_standby,
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.pwr_domain_on = hikey960_pwr_domain_on,
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.pwr_domain_on_finish = hikey960_pwr_domain_on_finish,
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.pwr_domain_off = hikey960_pwr_domain_off,
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.pwr_domain_suspend = hikey960_pwr_domain_suspend,
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.pwr_domain_suspend_finish = hikey960_pwr_domain_suspend_finish,
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.system_off = hikey960_system_off,
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.system_reset = hikey960_system_reset,
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.validate_power_state = hikey960_validate_power_state,
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.validate_ns_entrypoint = hikey960_validate_ns_entrypoint,
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.get_sys_suspend_power_state = hikey960_get_sys_suspend_power_state,
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};
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int plat_setup_psci_ops(uintptr_t sec_entrypoint,
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const plat_psci_ops_t **psci_ops)
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{
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unsigned int id = 0;
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int ret;
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ret = hikey960_read_boardid(&id);
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if (ret == 0) {
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if (id == 5300U)
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uart_base = PL011_UART5_BASE;
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else
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uart_base = PL011_UART6_BASE;
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} else {
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uart_base = PL011_UART6_BASE;
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}
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hikey960_sec_entrypoint = sec_entrypoint;
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INFO("%s: sec_entrypoint=0x%lx\n", __func__,
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(unsigned long)hikey960_sec_entrypoint);
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/*
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* Initialize PSCI ops struct
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*/
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*psci_ops = &hikey960_psci_ops;
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return 0;
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}
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