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c3cf06f1a3
All identifiers, regardless of use, that start with two underscores are reserved. This means they can't be used in header guards. The style that this project is now to use the full name of the file in capital letters followed by 'H'. For example, for a file called "uart_example.h", the header guard is UART_EXAMPLE_H. The exceptions are files that are imported from other projects: - CryptoCell driver - dt-bindings folders - zlib headers Change-Id: I50561bf6c88b491ec440d0c8385c74650f3c106e Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
328 lines
13 KiB
C
328 lines
13 KiB
C
/*
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* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef HISI_SRAM_MAP_H
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#define HISI_SRAM_MAP_H
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/*
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* SRAM Memory Region Layout
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*
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* +-----------------------+
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* | Low Power Mode | 7KB
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* +-----------------------+
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* | Secure OS | 64KB
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* +-----------------------+
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* | Software Flag | 1KB
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* +-----------------------+
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*
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*/
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#define SOC_SRAM_OFF_BASE_ADDR (0xFFF80000)
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/* PM Section: 7KB */
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#define SRAM_PM_ADDR (SOC_SRAM_OFF_BASE_ADDR)
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#define SRAM_PM_SIZE (0x00001C00)
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/* TEE OS Section: 64KB */
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#define SRAM_TEEOS_ADDR (SRAM_PM_ADDR + SRAM_PM_SIZE)
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#define SRAM_TEEOS_SIZE (0x00010000)
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/* General Use Section: 1KB */
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#define SRAM_GENERAL_ADDR (SRAM_TEEOS_ADDR + SRAM_TEEOS_SIZE)
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#define SRAM_GENERAL_SIZE (0x00000400)
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/*
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* General Usage Section Layout:
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*
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* +-----------------------+
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* | AP boot flag | 64B
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* +-----------------------+
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* | DICC flag | 32B
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* +-----------------------+
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* | Soft flag | 256B
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* +-----------------------+
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* | Thermal flag | 128B
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* +-----------------------+
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* | CSHELL | 4B
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* +-----------------------+
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* | Uart Switching | 4B
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* +-----------------------+
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* | ICC | 1024B
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* +-----------------------+
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* | Memory Management | 1024B
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* +-----------------------+
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* | IFC | 32B
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* +-----------------------+
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* | HIFI | 32B
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* +-----------------------+
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* | DDR capacity | 4B
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* +-----------------------+
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* | Reserved |
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* +-----------------------+
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*
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*/
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/* App Core Boot Flags */
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#define MEMORY_AXI_ACPU_START_ADDR (SRAM_GENERAL_ADDR)
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#define MEMORY_AXI_ACPU_START_SIZE (64)
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#define MEMORY_AXI_SRESET_FLAG_ADDR (MEMORY_AXI_ACPU_START_ADDR + 0x0000)
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#define MEMORY_AXI_SECOND_CPU_BOOT_ADDR (MEMORY_AXI_ACPU_START_ADDR + 0x0004)
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#define MEMORY_AXI_READY_FLAG_ADDR (MEMORY_AXI_ACPU_START_ADDR + 0x0008)
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#define MEMORY_AXI_FASTBOOT_ENTRY_ADDR (MEMORY_AXI_ACPU_START_ADDR + 0x000C)
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#define MEMORY_AXI_PD_CHARGE_ADDR (MEMORY_AXI_ACPU_START_ADDR + 0x0010)
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#define MEMORY_AXI_DBG_ALARM_ADDR (MEMORY_AXI_ACPU_START_ADDR + 0x0014)
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#define MEMORY_AXI_CHIP_ADDR (MEMORY_AXI_ACPU_START_ADDR + 0x0018)
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#define MEMORY_AXI_BOARD_TYPE_ADDR (MEMORY_AXI_ACPU_START_ADDR + 0x001C)
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#define MEMORY_AXI_BOARD_ID_ADDR (MEMORY_AXI_ACPU_START_ADDR + 0x0020)
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#define MEMORY_AXI_CHARGETYPE_FLAG_ADDR (MEMORY_AXI_ACPU_START_ADDR + 0x0024)
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#define MEMORY_AXI_COLD_START_ADDR (MEMORY_AXI_ACPU_START_ADDR + 0x0028)
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#define MEMORY_AXI_ANDROID_REBOOT_FLAG_ADDR (MEMORY_AXI_ACPU_START_ADDR + 0x002C)
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#define MEMORY_AXI_ACPU_WDTRST_REBOOT_FLAG_ADDR (MEMORY_AXI_ACPU_START_ADDR + 0x0030)
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#define MEMORY_AXI_ABNRST_BITMAP_ADDR (MEMORY_AXI_ACPU_START_ADDR + 0x0034)
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#define MEMORY_AXI_32K_CLK_TYPE_ADDR (MEMORY_AXI_ACPU_START_ADDR + 0x0038)
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#define AXI_MODEM_PANIC_FLAG_ADDR (MEMORY_AXI_ACPU_START_ADDR + 0x003C)
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#define AXI_MODEM_PANIC_FLAG (0x68697369)
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#define MEMORY_AXI_ACPU_END_ADDR (AXI_MODEM_PANIC_FLAG_ADDR + 4)
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/* DICC Flags */
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#define MEMORY_AXI_DICC_ADDR (MEMORY_AXI_ACPU_START_ADDR + MEMORY_AXI_ACPU_START_SIZE)
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#define MEMORY_AXI_DICC_SIZE (32)
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#define MEMORY_AXI_SOFT_FLAG_ADDR (MEMORY_AXI_DICC_ADDR + MEMORY_AXI_DICC_SIZE)
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#define MEMORY_AXI_SOFT_FLAG_SIZE (256)
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/* Thermal Flags */
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#define MEMORY_AXI_TEMP_PROTECT_ADDR (MEMORY_AXI_SOFT_FLAG_ADDR + MEMORY_AXI_SOFT_FLAG_SIZE)
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#define MEMORY_AXI_TEMP_PROTECT_SIZE (128)
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/* CSHELL */
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#define MEMORY_AXI_USB_CSHELL_ADDR (MEMORY_AXI_TEMP_PROTECT_ADDR + MEMORY_AXI_TEMP_PROTECT_SIZE)
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#define MEMORY_AXI_USB_CSHELL_SIZE (4)
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/* Uart and A/C Shell Switch Flags */
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#define MEMORY_AXI_UART_INOUT_ADDR (MEMORY_AXI_USB_CSHELL_ADDR + MEMORY_AXI_USB_CSHELL_SIZE)
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#define MEMORY_AXI_UART_INOUT_SIZE (4)
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/* IFC Flags */
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#define MEMORY_AXI_IFC_ADDR (MEMORY_AXI_UART_INOUT_ADDR + MEMORY_AXI_UART_INOUT_SIZE)
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#define MEMORY_AXI_IFC_SIZE (32)
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/* HIFI Data */
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#define MEMORY_AXI_HIFI_ADDR (MEMORY_AXI_IFC_ADDR + MEMORY_AXI_IFC_SIZE)
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#define MEMORY_AXI_HIFI_SIZE (32)
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/* CONFIG Flags */
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#define MEMORY_AXI_CONFIG_ADDR (MEMORY_AXI_HIFI_ADDR + MEMORY_AXI_HIFI_SIZE)
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#define MEMORY_AXI_CONFIG_SIZE (32)
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/* DDR Capacity Flags */
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#define MEMORY_AXI_DDR_CAPACITY_ADDR (MEMORY_AXI_CONFIG_ADDR + MEMORY_AXI_CONFIG_SIZE)
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#define MEMORY_AXI_DDR_CAPACITY_SIZE (4)
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/* USB Shell Flags */
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#define MEMORY_AXI_USB_SHELL_FLAG_ADDR (MEMORY_AXI_DDR_CAPACITY_ADDR + MEMORY_AXI_DDR_CAPACITY_SIZE)
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#define MEMORY_AXI_USB_SHELL_FLAG_SIZE (4)
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/* MCU WDT Switch Flag */
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#define MEMORY_AXI_MCU_WDT_FLAG_ADDR (MEMORY_AXI_USB_SHELL_FLAG_ADDR + MEMORY_AXI_USB_SHELL_FLAG_SIZE)
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#define MEMORY_AXI_MCU_WDT_FLAG_SIZE (4)
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/* TLDSP Mailbox MNTN */
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#define SRAM_DSP_MNTN_INFO_ADDR (MEMORY_AXI_MCU_WDT_FLAG_ADDR + MEMORY_AXI_MCU_WDT_FLAG_SIZE)
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#define SRAM_DSP_MNTN_SIZE (32)
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/* TLDSP ARM Mailbox Protect Flag */
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#define SRAM_DSP_ARM_MAILBOX_PROTECT_FLAG_ADDR (SRAM_DSP_MNTN_INFO_ADDR + SRAM_DSP_MNTN_SIZE)
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#define SRAM_DSP_ARM_MAILBOX_PROTECT_FLAG_SIZE (4)
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/* RTT Sleep Flag */
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#define SRAM_RTT_SLEEP_FLAG_ADDR (SRAM_DSP_ARM_MAILBOX_PROTECT_FLAG_ADDR + SRAM_DSP_ARM_MAILBOX_PROTECT_FLAG_SIZE)
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#define SRAM_RTT_SLEEP_FLAG_SIZE (32)
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/* LDSP Awake Flag */
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#define MEMORY_AXI_LDSP_AWAKE_ADDR (SRAM_RTT_SLEEP_FLAG_ADDR + SRAM_RTT_SLEEP_FLAG_SIZE)
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#define MEMORY_AXI_LDSP_AWAKE_SIZE (4)
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#define NVUPDATE_SUCCESS 0x5555AAAA
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#define NVUPDATE_FAILURE 0xAAAA5555
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/*
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* Low Power Mode Region
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*/
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#define PWRCTRL_ACPU_ASM_SPACE_ADDR (SRAM_PM_ADDR)
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#define PWRCTRL_ACPU_ASM_SPACE_SIZE (SRAM_PM_SIZE)
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#define PWRCTRL_ACPU_ASM_MEM_BASE (PWRCTRL_ACPU_ASM_SPACE_ADDR)
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#define PWRCTRL_ACPU_ASM_MEM_SIZE (PWRCTRL_ACPU_ASM_SPACE_SIZE)
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#define PWRCTRL_ACPU_ASM_CODE_BASE (PWRCTRL_ACPU_ASM_MEM_BASE + 0x200)
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#define PWRCTRL_ACPU_ASM_DATA_BASE (PWRCTRL_ACPU_ASM_MEM_BASE + 0xE00)
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#define PWRCTRL_ACPU_ASM_DATA_SIZE (0xE00)
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#define PWRCTRL_ACPU_ASM_D_C0_ADDR (PWRCTRL_ACPU_ASM_DATA_BASE)
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#define PWRCTRL_ACPU_ASM_D_C0_MMU_PARA_AD (PWRCTRL_ACPU_ASM_DATA_BASE + 0)
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#define PWRCTRL_ACPU_ASM_D_ARM_PARA_AD (PWRCTRL_ACPU_ASM_DATA_BASE + 0x20)
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#define PWRCTRL_ACPU_ASM_D_COMM_ADDR (PWRCTRL_ACPU_ASM_DATA_BASE + 0x700)
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#define PWRCTRL_ACPU_REBOOT (PWRCTRL_ACPU_ASM_D_COMM_ADDR)
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#define PWRCTRL_ACPU_REBOOT_SIZE (0x200)
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#define PWRCTRL_ACPU_ASM_SLICE_BAK_ADDR (PWRCTRL_ACPU_REBOOT + PWRCTRL_ACPU_REBOOT_SIZE)
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#define PWRCTRL_ACPU_ASM_SLICE_BAK_SIZE (4)
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#define PWRCTRL_ACPU_ASM_DEBUG_FLAG_ADDR (PWRCTRL_ACPU_ASM_SLICE_BAK_ADDR + PWRCTRL_ACPU_ASM_SLICE_BAK_SIZE)
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#define PWRCTRL_ACPU_ASM_DEBUG_FLAG_SIZE (4)
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#define EXCH_A_CORE_POWRCTRL_CONV_ADDR (PWRCTRL_ACPU_ASM_DEBUG_FLAG_ADDR + PWRCTRL_ACPU_ASM_DEBUG_FLAG_SIZE)
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#define EXCH_A_CORE_POWRCTRL_CONV_SIZE (4)
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/*
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* Below region memory mapping is:
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* 4 + 12 + 16 + 28 + 28 + 16 + 28 + 12 + 24 + 20 + 64 +
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* 4 + 4 + 4 + 4 + 12 + 4 + 4 + 4 + 4 + 16 + 4 + 0x2BC +
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* 24 + 20 + 12 + 16
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*/
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#define MEMORY_AXI_CPU_IDLE_ADDR (EXCH_A_CORE_POWRCTRL_CONV_ADDR + EXCH_A_CORE_POWRCTRL_CONV_SIZE)
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#define MEMORY_AXI_CPU_IDLE_SIZE (4)
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#define MEMORY_AXI_CUR_FREQ_ADDR (MEMORY_AXI_CPU_IDLE_ADDR + MEMORY_AXI_CPU_IDLE_SIZE)
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#define MEMORY_AXI_CUR_FREQ_SIZE (12)
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#define MEMORY_AXI_ACPU_FREQ_VOL_ADDR (MEMORY_AXI_CUR_FREQ_ADDR + MEMORY_AXI_CUR_FREQ_SIZE)
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#define MEMORY_AXI_ACPU_FREQ_VOL_SIZE (16 + 28 + 28)
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#define MEMORY_AXI_DDR_FREQ_VOL_ADDR (MEMORY_AXI_ACPU_FREQ_VOL_ADDR + MEMORY_AXI_ACPU_FREQ_VOL_SIZE)
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#define MEMORY_AXI_DDR_FREQ_VOL_SIZE (16 + 28)
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#define MEMORY_AXI_ACPU_FIQ_TEST_ADDR (MEMORY_AXI_DDR_FREQ_VOL_ADDR + MEMORY_AXI_DDR_FREQ_VOL_SIZE)
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#define MEMORY_AXI_ACPU_FIQ_TEST_SIZE (12)
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#define MEMORY_AXI_ACPU_FIQ_CPU_INFO_ADDR (MEMORY_AXI_ACPU_FIQ_TEST_ADDR + MEMORY_AXI_ACPU_FIQ_TEST_SIZE)
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#define MEMORY_AXI_ACPU_FIQ_CPU_INFO_SIZE (24)
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#define MEMORY_AXI_ACPU_FIQ_DEBUG_INFO_ADDR (MEMORY_AXI_ACPU_FIQ_CPU_INFO_ADDR + MEMORY_AXI_ACPU_FIQ_CPU_INFO_SIZE)
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#define MEMORY_AXI_ACPU_FIQ_DEBUG_INFO_SIZE (20)
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#define MEMORY_FREQDUMP_ADDR (MEMORY_AXI_ACPU_FIQ_DEBUG_INFO_ADDR + MEMORY_AXI_ACPU_FIQ_DEBUG_INFO_SIZE)
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#define MEMORY_FREQDUMP_SIZE (64)
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#define MEMORY_AXI_CCPU_LOG_ADDR (MEMORY_FREQDUMP_ADDR + MEMORY_FREQDUMP_SIZE)
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#define MEMORY_AXI_CCPU_LOG_SIZE (4)
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#define MEMORY_AXI_MCU_LOG_ADDR (MEMORY_AXI_CCPU_LOG_ADDR + MEMORY_AXI_CCPU_LOG_SIZE)
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#define MEMORY_AXI_MCU_LOG_SIZE (4)
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#define MEMORY_AXI_SEC_CORE_BOOT_ADDR (MEMORY_AXI_MCU_LOG_ADDR + MEMORY_AXI_MCU_LOG_SIZE)
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#define MEMORY_AXI_SEC_CORE_BOOT_SIZE (4)
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#define MEMORY_AXI_BBP_PS_VOTE_FLAG_ADDR (MEMORY_AXI_SEC_CORE_BOOT_ADDR + MEMORY_AXI_SEC_CORE_BOOT_SIZE)
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#define MEMORY_AXI_BBP_PS_VOTE_FLAG_SIZE (0x4)
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#define POLICY_AREA_RESERVED (MEMORY_AXI_BBP_PS_VOTE_FLAG_ADDR + MEMORY_AXI_BBP_PS_VOTE_FLAG_SIZE)
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#define POLICY_AREA_RESERVED_SIZE (12)
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#define DDR_POLICY_VALID_MAGIC (POLICY_AREA_RESERVED + POLICY_AREA_RESERVED_SIZE)
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#define DDR_POLICY_VALID_MAGIC_SIZE (4)
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#define DDR_POLICY_MAX_NUM (DDR_POLICY_VALID_MAGIC + DDR_POLICY_VALID_MAGIC_SIZE)
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#define DDR_POLICY_MAX_NUM_SIZE (4)
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#define DDR_POLICY_SUPPORT_NUM (DDR_POLICY_MAX_NUM + DDR_POLICY_MAX_NUM_SIZE)
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#define DDR_POLICY_SUPPORT_NUM_SIZE (4)
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#define DDR_POLICY_CUR_POLICY (DDR_POLICY_SUPPORT_NUM + DDR_POLICY_SUPPORT_NUM_SIZE)
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#define DDR_POLICY_CUR_POLICY_SIZE (4)
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#define ACPU_POLICY_VALID_MAGIC (DDR_POLICY_CUR_POLICY + DDR_POLICY_CUR_POLICY_SIZE)
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#define ACPU_POLICY_VALID_MAGIC_SIZE (4)
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#define ACPU_POLICY_MAX_NUM (ACPU_POLICY_VALID_MAGIC + ACPU_POLICY_VALID_MAGIC_SIZE)
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#define ACPU_POLICY_MAX_NUM_SIZE (4)
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#define ACPU_POLICY_SUPPORT_NUM (ACPU_POLICY_MAX_NUM + ACPU_POLICY_MAX_NUM_SIZE)
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#define ACPU_POLICY_SUPPORT_NUM_SIZE (4)
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#define ACPU_POLICY_CUR_POLICY (ACPU_POLICY_SUPPORT_NUM + ACPU_POLICY_SUPPORT_NUM_SIZE)
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#define ACPU_POLICY_CUR_POLICY_SIZE (4)
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#define LPDDR_OPTION_ADDR (ACPU_POLICY_CUR_POLICY + ACPU_POLICY_CUR_POLICY_SIZE)
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#define LPDDR_OPTION_SIZE (4)
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#define MEMORY_AXI_DDR_DDL_ADDR (LPDDR_OPTION_ADDR + LPDDR_OPTION_SIZE)
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#define MEMORY_AXI_DDR_DDL_SIZE (0x2BC)
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#define DDR_TEST_DFS_ADDR (MEMORY_AXI_DDR_DDL_ADDR + MEMORY_AXI_DDR_DDL_SIZE)
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#define DDR_TEST_DFS_ADDR_SIZE (4)
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#define DDR_TEST_DFS_TIMES_ADDR (DDR_TEST_DFS_ADDR + DDR_TEST_DFS_ADDR_SIZE)
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#define DDR_TEST_DFS_TIMES_ADDR_SIZE (4)
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#define DDR_TEST_QOS_ADDR (DDR_TEST_DFS_TIMES_ADDR + DDR_TEST_DFS_TIMES_ADDR_SIZE)
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#define DDR_TEST_QOS_ADDR_SIZE (4)
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#define DDR_TEST_FUN_ADDR (DDR_TEST_QOS_ADDR + DDR_TEST_QOS_ADDR_SIZE)
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#define DDR_TEST_FUN_ADDR_SIZE (4)
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#define BOARD_TYPE_ADDR (DDR_TEST_FUN_ADDR + DDR_TEST_FUN_ADDR_SIZE)
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#define BOARD_ADDR_SIZE (4)
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#define DDR_DFS_FREQ_ADDR (BOARD_TYPE_ADDR + BOARD_ADDR_SIZE)
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#define DDR_DFS_FREQ_SIZE (4)
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#define DDR_PASR_ADDR (DDR_DFS_FREQ_ADDR + DDR_DFS_FREQ_SIZE)
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#define DDR_PASR_SIZE (20)
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#define ACPU_DFS_FREQ_ADDR (DDR_PASR_ADDR + DDR_PASR_SIZE)
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#define ACPU_DFS_FREQ_ADDR_SIZE (12)
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#define ACPU_CHIP_MAX_FREQ (ACPU_DFS_FREQ_ADDR + ACPU_DFS_FREQ_ADDR_SIZE)
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#define ACPU_CHIP_MAX_FREQ_SIZE (4)
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#define MEMORY_MEDPLL_STATE_ADDR (ACPU_CHIP_MAX_FREQ + ACPU_CHIP_MAX_FREQ_SIZE)
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#define MEMORY_MEDPLL_STATE_SIZE (8)
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#define MEMORY_CCPU_LOAD_FLAG_ADDR (MEMORY_MEDPLL_STATE_ADDR + MEMORY_MEDPLL_STATE_SIZE)
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#define MEMORY_CCPU_LOAD_FLAG_SIZE (4)
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#define ACPU_CORE_BITS_ADDR (MEMORY_CCPU_LOAD_FLAG_ADDR + MEMORY_CCPU_LOAD_FLAG_SIZE)
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#define ACPU_CORE_BITS_SIZE (4)
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#define ACPU_CLUSTER_IDLE_ADDR (ACPU_CORE_BITS_ADDR + ACPU_CORE_BITS_SIZE)
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#define ACPU_CLUSTER_IDLE_SIZE (4)
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#define ACPU_A53_FLAGS_ADDR (ACPU_CLUSTER_IDLE_ADDR + ACPU_CLUSTER_IDLE_SIZE)
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#define ACPU_A53_FLAGS_SIZE (4)
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#define ACPU_POWER_STATE_QOS_ADDR (ACPU_A53_FLAGS_ADDR+ACPU_A53_FLAGS_SIZE)
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#define ACPU_POWER_STATE_QOS_SIZE (4)
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#define ACPU_UNLOCK_CORE_FLAGS_ADDR (ACPU_POWER_STATE_QOS_ADDR+ACPU_POWER_STATE_QOS_SIZE)
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#define ACPU_UNLOCK_CORE_FLAGS_SIZE (8)
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#define ACPU_SUBSYS_POWERDOWN_FLAGS_ADDR (ACPU_UNLOCK_CORE_FLAGS_ADDR + ACPU_UNLOCK_CORE_FLAGS_SIZE)
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#define ACPU_SUBSYS_POWERDOWN_FLAGS_SIZE (4)
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#define ACPU_CORE_POWERDOWN_FLAGS_ADDR (ACPU_SUBSYS_POWERDOWN_FLAGS_ADDR + ACPU_SUBSYS_POWERDOWN_FLAGS_SIZE)
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#define ACPU_CORE_POWERDOWN_FLAGS_SIZE (4)
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#define ACPU_CLUSTER_POWERDOWN_FLAGS_ADDR (ACPU_CORE_POWERDOWN_FLAGS_ADDR + ACPU_CORE_POWERDOWN_FLAGS_SIZE)
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#define ACPU_CLUSTER_POWERDOWN_FLAGS_SIZE (4)
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#define ACPU_ARM64_FLAGA (ACPU_CLUSTER_POWERDOWN_FLAGS_ADDR + ACPU_CLUSTER_POWERDOWN_FLAGS_SIZE)
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#define ACPU_ARM64_FLAGA_SIZE (4)
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#define ACPU_ARM64_FLAGB (ACPU_ARM64_FLAGA + ACPU_ARM64_FLAGA_SIZE)
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#define ACPU_ARM64_FLAGB_SIZE (4)
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#define MCU_EXCEPTION_FLAGS_ADDR (ACPU_ARM64_FLAGB + ACPU_ARM64_FLAGB_SIZE)
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#define MCU_EXCEPTION_FLAGS_SIZE (4)
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#define ACPU_MASTER_CORE_STATE_ADDR (MCU_EXCEPTION_FLAGS_ADDR + MCU_EXCEPTION_FLAGS_SIZE)
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#define ACPU_MASTER_CORE_STATE_SIZE (4)
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#define PWRCTRL_AXI_RESERVED_ADDR (ACPU_MASTER_CORE_STATE_ADDR + ACPU_MASTER_CORE_STATE_SIZE)
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#endif /* HISI_SRAM_MAP_H */
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