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09d40e0e08
Enforce full include path for includes. Deprecate old paths.
The following folders inside include/lib have been left unchanged:
- include/lib/cpus/${ARCH}
- include/lib/el3_runtime/${ARCH}
The reason for this change is that having a global namespace for
includes isn't a good idea. It defeats one of the advantages of having
folders and it introduces problems that are sometimes subtle (because
you may not know the header you are actually including if there are two
of them).
For example, this patch had to be created because two headers were
called the same way: e0ea0928d5 ("Fix gpio includes of mt8173 platform
to avoid collision."). More recently, this patch has had similar
problems: 46f9b2c3a2 ("drivers: add tzc380 support").
This problem was introduced in commit 4ecca33988 ("Move include and
source files to logical locations"). At that time, there weren't too
many headers so it wasn't a real issue. However, time has shown that
this creates problems.
Platforms that want to preserve the way they include headers may add the
removed paths to PLAT_INCLUDES, but this is discouraged.
Change-Id: I39dc53ed98f9e297a5966e723d1936d6ccf2fc8f
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
105 lines
2.8 KiB
C
105 lines
2.8 KiB
C
/*
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* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <stdarg.h>
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#include <stdio.h>
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#include <string.h>
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#include <platform_def.h>
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#include <common/debug.h>
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#include <lib/mmio.h>
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#include <hi6220_regs_acpu.h>
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#include <hi6220_regs_ao.h>
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#include <hisi_ipc.h>
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#include <hisi_pwrc.h>
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#include <hisi_sram_map.h>
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#define CLUSTER_CORE_COUNT (4)
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#define CLUSTER_CORE_MASK ((1 << CLUSTER_CORE_COUNT) - 1)
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void hisi_pwrc_set_core_bx_addr(unsigned int core, unsigned int cluster,
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uintptr_t entry_point)
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{
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uintptr_t *core_entry = (uintptr_t *)PWRCTRL_ACPU_ASM_D_ARM_PARA_AD;
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unsigned int i;
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if (!core_entry) {
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INFO("%s: core entry point is null!\n", __func__);
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return;
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}
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i = cluster * CLUSTER_CORE_COUNT + core;
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mmio_write_64((uintptr_t)(core_entry + i), entry_point);
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}
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void hisi_pwrc_set_cluster_wfi(unsigned int cluster)
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{
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unsigned int reg = 0;
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if (cluster == 0) {
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reg = mmio_read_32(ACPU_SC_SNOOP_PWD);
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reg |= PD_DETECT_START0;
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mmio_write_32(ACPU_SC_SNOOP_PWD, reg);
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} else if (cluster == 1) {
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reg = mmio_read_32(ACPU_SC_SNOOP_PWD);
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reg |= PD_DETECT_START1;
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mmio_write_32(ACPU_SC_SNOOP_PWD, reg);
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}
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}
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void hisi_pwrc_enable_debug(unsigned int core, unsigned int cluster)
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{
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unsigned int val, enable;
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enable = 1U << (core + PDBGUP_CLUSTER1_SHIFT * cluster);
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/* Enable debug module */
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val = mmio_read_32(ACPU_SC_PDBGUP_MBIST);
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mmio_write_32(ACPU_SC_PDBGUP_MBIST, val | enable);
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do {
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/* RAW barrier */
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val = mmio_read_32(ACPU_SC_PDBGUP_MBIST);
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} while (!(val & enable));
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}
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int hisi_pwrc_setup(void)
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{
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unsigned int reg, sec_entrypoint;
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extern char pm_asm_code[], pm_asm_code_end[];
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extern char v7_asm[], v7_asm_end[];
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sec_entrypoint = PWRCTRL_ACPU_ASM_CODE_BASE;
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mmio_write_32(ACPU_SC_CPUx_RVBARADDR(0), sec_entrypoint >> 2);
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mmio_write_32(ACPU_SC_CPUx_RVBARADDR(1), sec_entrypoint >> 2);
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mmio_write_32(ACPU_SC_CPUx_RVBARADDR(2), sec_entrypoint >> 2);
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mmio_write_32(ACPU_SC_CPUx_RVBARADDR(3), sec_entrypoint >> 2);
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mmio_write_32(ACPU_SC_CPUx_RVBARADDR(4), sec_entrypoint >> 2);
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mmio_write_32(ACPU_SC_CPUx_RVBARADDR(5), sec_entrypoint >> 2);
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mmio_write_32(ACPU_SC_CPUx_RVBARADDR(6), sec_entrypoint >> 2);
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mmio_write_32(ACPU_SC_CPUx_RVBARADDR(7), sec_entrypoint >> 2);
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memset((void *)PWRCTRL_ACPU_ASM_SPACE_ADDR, 0, 0x400);
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memcpy((void *)PWRCTRL_ACPU_ASM_SPACE_ADDR, (void *)v7_asm,
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v7_asm_end - v7_asm);
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memcpy((void *)PWRCTRL_ACPU_ASM_CODE_BASE, (void *)pm_asm_code,
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pm_asm_code_end - pm_asm_code);
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reg = mmio_read_32(AO_SC_SYS_CTRL1);
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/* Remap SRAM address for ACPU */
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reg |= AO_SC_SYS_CTRL1_REMAP_SRAM_AARM |
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AO_SC_SYS_CTRL1_REMAP_SRAM_AARM_MSK;
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/* Enable reset signal for watchdog */
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reg |= AO_SC_SYS_CTRL1_AARM_WD_RST_CFG |
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AO_SC_SYS_CTRL1_AARM_WD_RST_CFG_MSK;
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mmio_write_32(AO_SC_SYS_CTRL1, reg);
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return 0;
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}
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